Abstract: A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portions 2, and a second insulating layer 46. The stacked body includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second staircase portions 2 are provided in a first end portion 101 a second end region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) in the X-direction direction. A length L1 in the X-direction of the second insulating layer 46 is longer than a length L2 in the x-direction of the second electrode layer 41 (SGD) and shorter than a length L3 in the X-direction of the first electrode layer 41 (WLDD).

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

Abstract: A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. The plurality of electrode layers includes a first electrode layer connected to a first wire in the first wiring layer and a second electrode layer connected to a second wire in the second wiring layer.

Abstract: A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.

Abstract: A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.

Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, an electrode layer provided above the substrate, a first insulating layer provided on the electrode layer, a stacked body provided on the insulating layer, a memory film, a channel body layer, a channel body connecting portion and a second insulating layer. The stacked body has a plurality of conductive layers and a plurality of insulating film alternately stacked on each other. The memory film is provided on a sidewall of each of a pair of holes penetrating the stacked body in a direction of stacking the stacked body. The channel body layer is provided on an inner side of the memory film in each of the pair of the holes.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, an electrode layer provided above the substrate, a first insulating layer provided on the electrode layer, a stacked body provided on the insulating layer, a memory film, a channel body layer, a channel body connecting portion and a second insulating layer. The stacked body has a plurality of conductive layers and a plurality of insulating film alternately stacked on each other. The memory film is provided on a sidewall of each of a pair of holes penetrating the stacked body in a direction of stacking the stacked body. The channel body layer is provided on an inner side of the memory film in each of the pair of the holes.

Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a resistance element of a first conductivity type formed in one region of the semiconductor substrate; a field effect transistor of a second conductivity type formed in another region of the semiconductor substrate; and a field effect transistor of the first conductivity type formed in still another region of the semiconductor substrate. The resistance element includes: an insulating film formed in an upper layer portion of the semiconductor substrate; and a well of the first conductivity type formed immediately below the insulating film, an impurity concentration at an arbitrary depth position in the well of the first conductivity is lower than an impurity concentration at the same depth position in a channel region of the field effect transistor of the second conductivity type.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a resistance element of a first conductivity type formed in one region of the semiconductor substrate; a field effect transistor of a second conductivity type formed in another region of the semiconductor substrate; and a field effect transistor of the first conductivity type formed in still another region of the semiconductor substrate. The resistance element includes: an insulating film formed in an upper layer portion of the semiconductor substrate; and a well of the first conductivity type formed immediately below the insulating film, an impurity concentration at an arbitrary depth position in the well of the first conductivity is lower than an impurity concentration at the same depth position in a channel region of the field effect transistor of the second conductivity type.