Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Abstract: A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This is made possible by positioning the adder elements at the first pipestage in each of the pipelines. Single width registers are used to hold the results of the initial add/subtract operation. Single bit registers pipeline the carry bits from the adders and incrementors to the next stage. The incrementor collects the sum from one of the adder elements, the pipelined carry bit from that adder element, and the carry bit from a previous stage adder and combines them to produce a new result and carry. This new result is passed along the pipeline to the output bus of the circuit. In this fashion, no double width busses or registers are required in between individual pipestages of the pipelines.

Abstract: A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B) communicating the lookahead carry output of each of the logic blocks to a carry input of a next logic block; (C) presenting the lookahead carry output of a last logic block as the carry-out.

Abstract: A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.

Abstract: An apparatus comprising one or more look-up-tables (LUTs). The LUTs may be configured to provide logical functions. The one or more LUTs are generally implemented within a multiport memory.

Abstract: A method and system for routing signals through interconnect matrices in a programmable logic device such that downstream routing failures can be reduced. In one embodiment, the invention is used to improve routing in complex programmable logic devices or CPLDs, however, the invention can be applied to other programmable devices and routing resources. In routing a set of signals through an upstream interconnect matrix or PIM, the method determines a set of high priority signals. In routing the upstream PIM, the method uses a Maximum Bipartite Matching process in one embodiment to route the original signals once. The duplicated high priority signals are then routed and sent to the input array of the downstream interconnect matrix along with the originally routed signals. From the originally routed signals and the duplicate signals, the downstream interconnect matrix routes each unique signal once and only once depending on the available routing resources.

Abstract: A circular product term allocator configured to provide connections for product term signals to macrocells of a programmable logic device is provided. The circular product term allocator may provide such connections through a logic OR function. Alternatively, a homogeneous product term allocator may be configured to provide connections for product term signals to macrocells of a programmable logic device. The homogeneous product term allocator may be configured to provide each of the product term signals to an equal number of macrocells. In yet another embodiment, a programmable logic device includes a plurality of macrocells and a product term allocator configured to provide an equal number of product term signals to each of the macrocells. In yet a further embodiment, a method of distributing product terms in a programmable logic device is accomplished by configuring a product term allocator to provide an equal number of product terms, but fewer than all of the product terms, to each of the macrocells.