Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing region with the one or more deposition precursors. The methods may include forming a silicon-containing material on the substrate. The methods may include providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material. The methods may include contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen.

Abstract: Systems and methods are disclosed for conducting an ultrasonic-based inspection. The systems and methods perform operations comprising: receiving a plurality of scan plan parameters associated with generating an image of at least one flaw within a specimen based on acoustic echo data obtained using full matrix capture (FMC); applying the plurality of scan plan parameters to an acoustic model, the acoustic model configured to determine a two-way pressure response of a plurality of inspection modes based on specular reflection and diffraction phenomena; generating, by the acoustic model based on the plurality of scan plan parameters, an acoustic region of influence (AROI) comprising an acoustic amplitude sensitivity map for a first inspection mode amongst the plurality of inspection modes; and generating, for display, a first image comprising the AROI associated with the first inspection mode for capturing or inspecting the image of the at least one flaw.

Abstract: Systems and methods are disclosed for conducting an ultrasonic-based inspection. The systems and methods perform operations comprising: receiving a plurality of scan plan parameters associated with generating an image of at least one flaw within a specimen based on acoustic echo data obtained using full matrix capture (FMC); applying the plurality of scan plan parameters to an acoustic model, the acoustic model configured to determine a two-way pressure response of a plurality of inspection modes based on specular reflection and diffraction phenomena; generating, by the acoustic model based on the plurality of scan plan parameters, an acoustic region of influence (AROI) comprising an acoustic amplitude sensitivity map for a first inspection mode amongst the plurality of inspection modes; and generating, for display, a first image comprising the AROI associated with the first inspection mode for capturing or inspecting the image of the at least one flaw.

Abstract: Systems and methods are disclosed for conducting an ultrasonic-based inspection. The systems and methods perform operations comprising: receiving a plurality of scan plan parameters associated with generating an image of at least one flaw within a specimen based on acoustic echo data obtained using full matrix capture (FMC); applying the plurality of scan plan parameters to an acoustic model, the acoustic model configured to determine a two-way pressure response of a plurality of inspection modes based on specular reflection and diffraction phenomena; generating, by the acoustic model based on the plurality of scan plan parameters, an acoustic region of influence (AROI) comprising an acoustic amplitude sensitivity map for a first inspection mode amongst the plurality of inspection modes; and generating, for display, a first image comprising the AROI associated with the first inspection mode for capturing or inspecting the image of the at least one flaw.

Abstract: Example embodiments of the present invention relate to a method and an apparatus for ultrasound imaging wherein transmitting elements of an ultrasonic array probe transmit ultrasound energy and receiving elements of the ultrasonic array probe receive received signals from the test object. The method includes deriving analytic signal values from the received signals, the analytic signal values being derived by applying a Hilbert transform to the received signals and performing a summation of multiple signal products derived by multiplication of a corresponding group of analytic signal values.

Abstract: Disclosed is an ultrasonic non-destructive testing and inspection system and method for determining acoustic velocities in a test object. Beams of acoustic energy from firing an element of an emitting probe propagate in a first wedge, and a beam incident at the critical angle generates a surface wave in the test object. The surface wave propagates to a second wedge and signals are received at receiving elements of a receiving probe array. When a set of appropriate delays is applied to the receiving elements, the acoustic time-of-flight is the same to all receiving elements. Determination of the appropriate delays and the times-of-flight for P-type surface waves and Rayleigh surface waves enables computation of the P- and S-wave acoustic velocities in the test object. The time-of-flight measurement also enables computation of the separation between the first and second wedges.

Abstract: Disclosed is an ultrasonic non-destructive testing and inspection system and method for determining acoustic velocities in a test object. Beams of acoustic energy from firing an element of an emitting probe propagate in a first wedge, and a beam incident at the critical angle generates a surface wave in the test object. The surface wave propagates to a second wedge and signals are received at receiving elements of a receiving probe array. When a set of appropriate delays is applied to the receiving elements, the acoustic time-of-flight is the same to all receiving elements. Determination of the appropriate delays and the times-of-flight for P-type surface waves and Rayleigh surface waves enables computation of the P- and S-wave acoustic velocities in the test object. The time-of-flight measurement also enables computation of the separation between the first and second wedges.

Abstract: A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block.

Abstract: A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block.

Abstract: The present invention minimizes the noise voltage associated with the switching of output driver transistors of integrated cicruits caused by the rapid change in value of the current, expressed by the term di/dt, from the load into the driver transistors through the package leads. The present invention uses a programmable coarse current control (CCC) circuit and a programmable fine current control (FCC) circuit that control the pull-down output transistors. The FCC creates two time periods, after which it prevents the CCC from controlling an output pull-down transistor. The FCC and the CCC are used to reduce the di/dt dependent voltage noise by controlling the slope and the shape of the output voltage pull-down characteristics.