Patents by Inventor Hang M. Liaw
Hang M. Liaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5520785Abstract: A method for enhancing aluminum nitride includes, in one version, annealing sputtered aluminum nitride in a reducing atmosphere (11), and subsequently annealing the sputtered aluminum nitride in an inert atmosphere (12). A superior aluminum nitride thin film (13) results. The films can withstand exposure to boiling water for times up to twenty minutes and maintain a refractive index, N.sub.f, greater than 2.0, and a preferred crystalline orientation ratio, I(002)/I(102), in excess of 1000.Type: GrantFiled: July 25, 1994Date of Patent: May 28, 1996Assignee: Motorola, Inc.Inventors: Keenan L. Evans, Hang M. Liaw, Jong-Kai Lin
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Patent number: 5430327Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.Type: GrantFiled: September 14, 1993Date of Patent: July 4, 1995Assignee: Motorola, Inc.Inventors: Schyi-Yi Wu, Hang M. Liaw, Curtis D. Moyer, Steven A. Voight, Israel A. Lesk
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Patent number: 5275971Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.Type: GrantFiled: April 20, 1992Date of Patent: January 4, 1994Assignee: Motorola, Inc.Inventors: Schyi-Yi Wu, Hang M. Liaw, Curtis D. Moyer, Steven A. Voight, Israel A. Lesk
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Patent number: 5272096Abstract: A layer of silicon carbide (33, 38, 41) is utilized in forming a bipolar transistor (30, 40). The transistor (30, 40) is formed on a substrate (31, 32) that has a single crystal silicon surface. The layer of silicon carbide (33, 38, 41) is epitaxially formed on the single crystal silicon surface. Thereafter, a layer of silicon (34) is epitaxially formed on the layer of silicon carbide (33, 38, 41). The silicon carbide (33, 38, 41) functions as an active transistor layer or alternately is within the transistor's depletion region.Type: GrantFiled: September 29, 1992Date of Patent: December 21, 1993Assignee: Motorola, Inc.Inventors: Edouard D. de Fresart, Hang M. Liaw
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Patent number: 5141887Abstract: A method of fabricating a low voltage, deep junction semiconductor device includes providing first and second wafers of opposite conductivity types, each having a dopant concentration of at least 4.0.times.10.sup.16 atoms/cc. After cleaning the wafers and removing heavy metal impurities therefrom by gettering, the wafers are bonded together. This method results in the successful fabrication of semiconductor devices having a junction depth in the range of 20 to 500 microns and a breakdown voltage of less than 20 volts.Type: GrantFiled: April 17, 1991Date of Patent: August 25, 1992Assignee: Motorola, Inc.Inventors: Hang M. Liaw, Frank S. d'Aragona, Raymond M. Roop, Dennis R. Olsen
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Patent number: 5108946Abstract: A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.Type: GrantFiled: July 27, 1990Date of Patent: April 28, 1992Assignee: Motorola, Inc.Inventors: Peter J. Zdebel, Barbara Vasquez, Hang M. Liaw, Christian A. Seelbach
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Patent number: 5080933Abstract: A method for selectively depositing polysilicon on a semiconductor surface (13) is accomplished by preparing the surface (13) in a manner to provide a contamination free surface. The contamination free semiconductor surface is placed into a chemical vapor deposition reactor. The semiconductor surface (13) is exposed to a single crystal inhibitor gas to prevent formation of single crystal silicon on surface (13). Semiconductor surface (13) is then exposed to a silicon containing gas with a hydrogen source to form the polysilicon.Type: GrantFiled: September 4, 1990Date of Patent: January 14, 1992Assignee: Motorola, Inc.Inventors: Melissa E. Grupen-Shemansky, Hang M. Liaw
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Patent number: 4963506Abstract: A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer having exposed silicon regions thereon is placed into a CVD reactor and subjected to a silicon containing gas and a halogen containing gas, at least one of which flows into the reactor with a hydrogen carrier gas. Amorphous silicon may be selectively deposited in the range of approximately 200 to 550 degrees centigrade while polycrystalline silicon may be selectively deposited in the range of approximately 550 to 750 degrees centigrade. It is also possible to deposit polycrystalline silicon at temperatures in the range of approximately 750 to 1000 degrees centigrade by employing another embodiment of the present invention.Type: GrantFiled: April 24, 1989Date of Patent: October 16, 1990Assignee: Motorola Inc.Inventors: Hang M. Liaw, Christian A. Seelbach
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Patent number: 4849371Abstract: A method and product for monocrystalline semiconductor buried layer contacts formed from recrystallized polycrystalline buried layers.Type: GrantFiled: November 15, 1988Date of Patent: July 18, 1989Assignee: Motorola Inc.Inventors: Kent W. Hansen, Frank S. D'Aragona, Hang M. Liaw
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Patent number: 4818323Abstract: A silicon wafer bonding technique is described utilizing low pressures and a dissolvable gas to substantially eliminate voids formed between the bonding surfaces of two wafers.Type: GrantFiled: June 26, 1987Date of Patent: April 4, 1989Assignee: Motorola Inc.Inventors: Frank S. d'Aragona, Hang M. Liaw
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Patent number: 4786615Abstract: A method for growing selective epitaxial silicon by chemical vapor deposition resulting in a substantially planar surface by growing superimposed silicon layers at temperatures above and below a transition point.Type: GrantFiled: August 31, 1987Date of Patent: November 22, 1988Assignee: Motorola Inc.Inventors: Hang M. Liaw, Ha T.-T. Nguyen
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Patent number: 4663831Abstract: Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.Type: GrantFiled: October 8, 1985Date of Patent: May 12, 1987Assignee: Motorola, Inc.Inventors: Mark S. Birrittella, Hang M. Liaw, Robert H. Reuss