Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Abstract: The present invention provides a memory configuration that is comprised of a memory controller, a single central switch, a data bus that is electrically coupled to the memory controller and the central switch, and a plurality of N memory modules, where each of the plurality of N memory modules is radially connected to the central switch by a corresponding memory module bus. The central switch is physically located on the motherboard and helps to provide in combination with the parallel connection of the memory modules, a point to point bus between the memory controller and the memory device on the memory module. The memory modules are field replaceable units and are electrically isolated from each other for use in high availability fault tolerant systems.

Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Abstract: A computer memory device featuring a high-bandwidth memory interface to transfer information between a controller and the memory cells of a memory modules. Bifurcated communication buses is provided to take advantage of the interface. One of the bifurcated communication busses is dedicated to data information transfer, dataLink, between the controller and the memory modules, with the remaining bus, commandLink, being dedicated to command/address information transfer therebetween. This facilitates communication between the controller and the memory modules using information packets, bifurcated into data packets and command/address packets. To that end, the interface circuitry includes encoded chip select techniques that employs slaveId comparison logic, a plurality of control registers and delay registers to regulate the synchronization of communication transfers over the commandLink and the dataLink, as well as a queue register in which the packets are temporarily stored.

Abstract: A memory system for minimizing the capacitive load of the memory data bus. The invention provides a digital memory system including a controller, a data bus in electrical communication with the controller, and memory devices. The controller operates to selectively couple one of the memory devices to the data bus when accessing a memory location in that memory device and to decouple that memory device from the data bus at other times. This selective coupling of the memory devices minimizes capacitive loading of the data bus. A method according to the includes establishing an electrical connection between one of the memory devices and the external circuit in response to a request from the external circuit to access a memory location in the memory device. Next, the requested access to the memory location is provided. Then the electrical connection between the memory device and the external circuit is broken after the access has been completed, thereby reducing capacitive loading of the external circuit.

Abstract: This disclosure provides a memory system and device for synchronizing response across multiple memory devices, whether arranged serially upon a single data bus, in parallel across multiple data busses, or both. A memory controller periodically configures the system by separately placing each memory chip into a configuration mode. While in this mode, the chip is polled by the controller along the corresponding data bus, and the chip responds with a reply. The controller uses this reply to compute elapsed time between polling and the reply. Using all of the chips, the controller determines the maximum response time, in terms of elapsed clock cycles. Based on this maximum time, and the individual response times for each chip, the controller then programs each chip with a number which defines chip-based delay for responses to data read operations. In this manner, successive data reads can be performed on successive clock cycles without awaiting prior completion of earlier data reads.