Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

Abstract: A coherence logic of a first core in a multi-core processor receives a request to send a cache line to a second core in the multi-core processor. In response to receiving the request, the coherence logic determines if the cache line is associated to a logically nonvolatile virtual page mapped to a nonvolatile physical page in a nonvolatile main memory. If so, the coherence logic flushes the cache line from the cache to the nonvolatile main memory and then sends the cache line to the second core.

Abstract: A technique includes performing an update to a location of a non-volatile memory. The update is created by execution of at least one machine executable instruction of a plurality of machine executable instructions. The technique includes using a processor-based machine to selectively track the update to allow recovery of the execution to a given consistency point based at least in part on whether the machine executable instruction(s) creating the update are located within a synchronized section of the plurality of machine executable instructions.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

Abstract: A method for performing memory operations is provided. One or more processors can determine that at least a portion of data stored in a cache memory of the one or more processors is to be stored in the main memory. One or more ranges of addresses of the main memory is determined that correspond to a plurality of cache lines in the cache memory. A set of cache lines corresponding to addresses in the one or more ranges of addresses is identified, so that data stored in the identified set can be stored in the main memory. For each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, data stored in that cache line is caused to be stored in the main memory.

Abstract: A parallel-code optimization system includes a Procedural Concurrency Graph (PCG) generator. The PCG generator produces an initial PCG of a computer program including parallel code, and determines a refined PCG from the initial PCG by applying concurrency-type refinements and interference-type refinements to the initial PCG. The initial PCG and the refined PCG include nodes and edges connecting pairs of the nodes. The nodes represent defined procedures in the parallel code, and each edge represents a may-happen-in-parallel relation, and is associated with a set of lvalues that represents the immediate interference between the corresponding pair of nodes.

Abstract: A log entry is created in persistent memory that represents a modification to a variable that resides in persistent memory. A log entry is created in persistent memory that represents a synchronization operation. A program-order based dynamic ordering relationship is created between two successive log entries within an execution entity. A synchronization-order based dynamic ordering relationship is created between two log entries corresponding to synchronization operations in concurrently executing distinct execution entities of said execution instance.

Abstract: A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.

Abstract: A parallel-code optimization system includes a siloed program reference-identifier and an intermediate representation (IR) updater. The siloed program reference identifier determines siloed program references in parallel code, wherein siloed program references are free of cross-thread interference. The IR updater modifies data-flow abstractions based on the identified siloed program references.

Abstract: A log entry is created in persistent memory that represents a modification to a variable that resides in persistent memory. A log entry is created in persistent memory that represents a synchronization operation. A program-order based dynamic ordering relationship is created between two successive log entries within an execution entity. A synchronization-order based dynamic ordering relationship is created between two log entries corresponding to synchronization operations in concurrently executing distinct execution entities of said execution instance.

Abstract: There is provided a computer-implemented method of performing ownership acquire policy selection. The method includes compiling an atomic section to generate an instrumented executable. The instrumented executable is configured to generate a runtime abort graph describing a plurality of computer memory accesses made by the instrumented executable. The method also includes selecting each of a plurality of policies based on the runtime abort graph. The plurality of policies include a first policy and a second policy. The first policy is different from the second policy. The method further includes compiling the atomic section to generate a modified executable. The modified executable is configured to perform the computer memory accesses according to the selected policies.

Abstract: A parallel-code optimization system includes a Procedural Concurrency Graph (PCG) generator. The PCG generator produces an initial PCG of a computer program including parallel code, and determines a refined PCG from the initial PCG by applying concurrency-type refinements and interference-type refinements to the initial PCG. The initial PCG and the refined PCG include nodes and edges connecting pairs of the nodes. The nodes represent defined procedures in the parallel code, and each edge represents a may-happen-in-parallel relation, and is associated with a set of lvalues that represents the immediate interference between the corresponding pair of nodes.

Abstract: A parallel-code optimization system includes a siloed program reference-identifier and an intermediate representation (IR) updater. The siloed program reference identifier determines siloed program references in parallel code, wherein siloed program references are free of cross-thread interference. The IR updater modifies data-flow abstractions based on the identified siloed program references.

Abstract: A process for machining a blank from all directions with a machine tool, such as a milling machine, involves the machining from all directions being based on a three-dimensional template. In a first step, the three-dimensional form and, if need be, also the surface finish of the three-dimensional template may be automatically measured, and the associated data may be saved. In a second step, a blank may be held by at least one clamping adapter and a first region is brought into its final, ready to use partial form by the machine tool or the milling machine using said data for numerical control. In a third step, the partially machined blank may be held by at least one clamping adapter in the first, finally machined region and the remaining region may be brought into its final, ready to use overall form by the same machine tool or milling machine.