Abstract: In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is connected to the circuit subunits by means of a connecting unit, test signals are generated for the electric circuit and response signals generated by the electric circuit in response to the test signals are evaluated. The test signals and the response signals are interchanged between the circuit subunits by means of at least one compression/decompression unit associated with at least one of the circuit subunits.

Abstract: A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.

Abstract: In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is connected to the circuit subunits by means of a connecting unit, test signals are generated for the electric circuit and response signals generated by the electric circuit in response to the test signals are evaluated. The test signals and the response signals are interchanged between the circuit subunits by means of at least one compression/decompression unit associated with at least one of the circuit subunits.

Abstract: An electronic circuit comprises a volatile memory unit and a non-volatile memory unit which stores a repair information related to the volatile memory unit. The non-volatile and volatile memory units are connected together by a connecting device and are formed as a single electronic module.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one calibration wafer (102) being automatically introduced into the test device (100) by means of a handling unit (103), calibration values of the test device (100) being determined by means of a control by a calibration sequence control unit (105), the calibration values determined being stored in a memory unit (106), the test device (100) being calibrated by means of the stored calibration values, the calibration wafer (102) being output from the calibrated test device (100), and at least one wafer (101) to be tested being introduced into the calibrated test device (100) by means of the handling unit (103) and being tested by a control by means of a test sequence control unit (104) in the calibrated test device (100), the stored calibration values being applied.

Abstract: A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.