Abstract: Methods and apparatus to select Tornado forward error correction parameters for delivery systems are disclosed. A disclosed example system includes a transmitter station comprising a processor to select a Tornado error correction parameter based on an error correction configuration for a file and to indicate to a receiver the selected Tornado error correction parameter, and a Tornado error correction circuit to encode the file based on the selected Tornado error correction parameter.

Abstract: Disclosed are methods and circuit configurations for reference frequency signal distribution circuitry that suppress unwanted spurious components introduced by way of RF signal leakage. The methods and circuitry may include relocating components of a buffer along a reference frequency signal path, thereby suppressing conductive and inductive components associated with RF leakage paths entering the circuitry. A filter also may be used after the buffer to suppress spurious components resulting from subsampling of unwanted tones in a phase frequency detector or intermodulation between the reference signal and interference tones in the signal-path of the buffer.

Abstract: A phase-locked loop includes a phase detector, a loop filter, a voltage controlled oscillator and a frequency divider arranged such that the phase detector generates a phase detector output signal as a function of a phase difference between the reference clock signal and the feedback signal; the loop filter generates a frequency control signal from the phase detector output signal; the voltage controlled oscillator generates a phase-locked loop output signal that has a frequency that is controlled by the frequency control signal; and the frequency divider generates the feedback signal from the phase-locked loop output signal.

Abstract: Disclosed are methods and circuit configurations for reference frequency signal distribution circuitry that suppress unwanted spurious components introduced by way of RF signal leakage. The methods and circuitry may include relocating components of a buffer along a reference frequency signal path, thereby suppressing conductive and inductive components associated with RF leakage paths entering the circuitry. A filter also may be used after the buffer to suppress spurious components resulting from subsampling of unwanted tones in a phase frequency detector or intermodulation between the reference signal and interference tones in the signal-path of the buffer.

Abstract: The present invention helps to mitigate and reduce the amount of interfering signals (e.g. RF leakage) that enter the phase detector of a phase locked loop by acting as a less than perfect sampler. This is accomplished by introducing a time jitter to the signal edges that enter the phase detector input. A phase detector can also be made to act as a less than perfect sampler by intentionally introducing an interfering signal. For example, a small interfering analog signal can be introduced with a different frequency from the reference frequency already present in the PLL. The interfering signal will cause the stable internal signal to vary slightly in time at the rate of the interfering signal frequency. It is this signal variation and jitter introduced on the signal edges entering the phase detector input that induces the phase detector to act as a less than perfect sampler.

Abstract: The present invention helps to mitigate and reduce the amount of interfering signals (e.g. RF leakage) that enter the phase detector of a phase locked loop by acting as a less than perfect sampler. This is accomplished by introducing a time jitter to the signal edges that enter the phase detector input. A phase detector can also be made to act as a less than perfect sampler by intentionally introducing an interfering signal. For example, a small interfering analog signal can be introduced with a different frequency from the reference frequency already present in the PLL. The interfering signal will cause the stable internal signal to vary slightly in time at the rate of the interfering signal frequency. It is this signal variation and jitter introduced on the signal edges entering the phase detector input that induces the phase detector to act as a less than perfect sampler.

Abstract: The present invention relates to a receiver device comprising a receiver (104) adapted to receive radio signals in two frequency bands (FB1, FB2). The radio signals in one of the frequency bands (FB1) constitute communication signals for a radio system (AMPS, NMT) having a certain channel spacing, whereas the radio signals of the second frequency band (FB2) constitutes communication signals for a second radio system (PCS1900, DCS1800, GSM) having a second certain channel spacing. The receiver (104) comprises two inputs (108, 11) each intended for a radio system having different frequency bands and channel spacing. For radio signals occurring on one input (108), mixing is performed from the RF range directly to the baseband frequency range. For radio signals occurring on the second input (108) the mixing from the radio frequency range to the baseband frequency range is carried out through an intermediate frequency range.

Abstract: A phase-locked loop bandwidth is tuned to a desired level by operating the phase-locked loop in a phase-locked condition at a first frequency and applying a step response to the phase-locked loop by causing the phase-locked loop to begin locking to a second frequency that is different from the first frequency. A parameter is then detected that is related to the applied step response and that is indicative of whether the phase-locked loop bandwidth is at the desired level. The phase-locked loop bandwidth is adjusted, and the steps of operating at the first frequency, applying the step response, detecting the parameter and adjusting the phase-locked loop bandwidth are repeated until the phase-locked loop bandwidth is at the desired level. Where the desired bandwidth level for tuning is not the operational bandwidth, the phase-locked loop bandwidth is further adjusted by a predetermined amount, thereby tuning the phase-locked loop bandwidth to an operational level.

Abstract: A multi-divide frequency divider, includes a chain of serially-connected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a first divisor, and each responding to a second state of the control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a second divisor. The output signal may be supplied to a successor frequency divider unit in the chain. Division by the first and second divisors causes the frequency divider to respectively transition through first and second predetermined state sequences.