Patents by Inventor Hans Hartung

Hans Hartung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071853
    Abstract: A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Hans Hartung, Martin Goldammer, Carsten Ehlers, Katja Engelkemeier, Guido Bönig
  • Publication number: 20230360989
    Abstract: A semiconductor module includes a power electronics carrier including a metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a volume of electrically insulating encapsulant that fills the interior volume and encapsulates the power semiconductor die, and a pressure compensation element disposed on or within the electrically insulating encapsulant, wherein the electrically insulating encapsulant is a liquid, wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant, and wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Inventors: Georg Troska, Hans Hartung
  • Publication number: 20230343661
    Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Georg Troska, Hans Hartung
  • Publication number: 20230014380
    Abstract: A semiconductor power module comprises an insulating interposer comprising an insulative layer disposed between a lower metal layer, a first upper metal layer and a second upper metal layer, a semiconductor transistor die disposed on the first upper metal layer, an electrical connector connecting the semiconductor transistor die with the second upper metal layer, a housing enclosing the insulating interposer and the semiconductor transistor die, a first potting material covering at least selective portions of the semiconductor transistor die and the electrical connector; and a second potting material applied onto the first potting material, wherein the first and second potting materials are different from each other.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 19, 2023
    Inventors: Hans Hartung, Martin Mayer, Edward Fuergut
  • Patent number: 11211307
    Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Georg Troska, Hans Hartung, Marianna Nomann
  • Publication number: 20200144154
    Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 7, 2020
    Inventors: Georg Troska, Hans Hartung, Marianna Nomann
  • Patent number: 10134654
    Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans Hartung, Reinhold Bayerer
  • Publication number: 20180033711
    Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate.
    Type: Application
    Filed: July 26, 2017
    Publication date: February 1, 2018
    Inventors: Hans Hartung, Reinhold Bayerer
  • Patent number: 9129934
    Abstract: A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 ?m. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25° C.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: September 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans Hartung, Dirk Siepe
  • Publication number: 20150001700
    Abstract: A module includes a base plate, a substrate having a first metallized side attached to the base plate and an opposing second metallized side, a power semiconductor die attached to the second metallized side of the substrate at a first side of the die, a first plurality of electrical connections between the second metallized side of the substrate and a second side of the die opposing the first side of the die, and a housing attached to a periphery of the base plate. The housing and base plate enclose the die and the first electrical connections. A second plurality of electrical connections extend from the second metallized side of the substrate through the housing to provide external electrical connections for the module. A parylene coating prevents gases and humidity from reaching the die, the first electrical connections, and the first metallized side of the substrate.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Hans Hartung, Johannes Uhlig, Christian Domesle
  • Publication number: 20110115068
    Abstract: A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 ?m. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25° C.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 19, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Hans Hartung, Dirk Siepe
  • Patent number: 7851334
    Abstract: An apparatus and method for producing semiconductor modules is disclosed. One embodiment provides for bonding at least one semiconductor die onto a carrier including a support film strip, the support film having applied an adhesive layer to one of its surfaces to attach the semiconductor die, and a pressure tool to press the semiconductor die and the support film strip onto the carrier to permanently contact the at least one semiconductor die to the carrier.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 14, 2010
    Assignee: Infineon Technologies AG
    Inventors: Roland Speckels, Karsten Guth, Hans Hartung
  • Publication number: 20090023250
    Abstract: An apparatus and method for producing semiconductor modules is disclosed. One embodiment provides for bonding at least one semiconductor die onto a carrier including a support film strip, the support film having applied an adhesive layer to one of its surfaces to attach the semiconductor die, and a pressure tool to press the semiconductor die and the support film strip onto the carrier to permanently contact the at least one semiconductor die to the carrier.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 22, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Roland Speckels, Karsten Guth, Hans Hartung
  • Publication number: 20070172598
    Abstract: The invention relates to a method for coating a metal bar (1), in particular a steel strap by hot dipping consisting in vertically passing the metal bar (1) through a container (2) containing a molten coating metal (3) and through a guiding channel (4) which is connected in series and has a predefined height (H). In order to retain the coating metal (2) in the container (3), an electromagnetic field is produced at the level of said guiding channel (4) by means of at least two inductors (5) which are arranged on two sides of the metal bar (1). In order to calm the coating bath, a predefined volume flow (Q) of the coating metal (2) is directed towards the guiding channel (4) at the level of the vertical extension (H) thereof. The inventive device for coating a metal bar by hot dipping is also disclosed.
    Type: Application
    Filed: March 18, 2004
    Publication date: July 26, 2007
    Inventors: Rolf Brisberger, Bernhard Tenckhoff, Holger Behrens, Hans Hartung
  • Publication number: 20070036908
    Abstract: The invention relates to a method for melt dip coating a metal strip (1), especially a steel strip (1a), which is guided through a coating station (4). The metal strip (1) is coated with a coating metal (3), the metal strip (1) is centrally maintained in a guide channel (8) in an electromagnetic sealing field (13) which seals the guide channel (8) from below and guides the metal strip (1) laterally, counter to ferromagnetic attraction, through a corrector field (14). The sealing field (13) is embodied as an electromagnetic guiding field (10), as a blocking field (11) or as a pump field (12) in order to select adequate lateral sealing when any particular sealing field (13) is used. Several corrector fields (14) are arranged in a distributed manner in a selected configuration, whereby the position and number thereof are determined individually at least according to the various widths of the metal strip (1).
    Type: Application
    Filed: February 13, 2004
    Publication date: February 15, 2007
    Inventors: Holger Behrens, Rolf Brisberger, Bodo Falkenhahn, Hans Hartung, Bernhard Tenckhoff, Walter Trakowski, Michael Zielenbach
  • Publication number: 20060108034
    Abstract: The invention relates to a method and device for descaling and/or cleaning a metal casting (1), particularly a hot-rolls trip made of normal steel or of stainless steel. According to the inventive method, the metal casting (1) is guided in a direction of conveyance (R) through a device (2), inside of which it is subjected to a plasma descaling and/or a plasma cleaning. In order to improve the result of the descaling or of the cleaning of the metal casting, the invention provides that before the device (2) for plasma descaling and/or plasma cleaning, in the direction of conveyance (R), the metal casting (1) is subjected to a process that imparts a high degree of flatness to the metal casting (1).
    Type: Application
    Filed: September 30, 2003
    Publication date: May 25, 2006
    Inventors: Klaus Frommann, Bodo Block, Rolf Brisberger, Hans Hartung
  • Publication number: 20050056068
    Abstract: A section straightening machine is operated by a method which involves passing the structural sections through the array of straightening tools. Section straightening forces are applied to adjustable shafts carrying the tools and adjusters at the service sides of the shaft applying forces acting counter to the section straightening forces.
    Type: Application
    Filed: October 27, 2004
    Publication date: March 17, 2005
    Inventors: Hans Hartung, Werner Kohlstedde, Markus Willems, Hans-Jurgen Reismann, Manfred Riffelmann, Ulrich Svejkovsky, Stefan Ernst