Abstract: Both the transmitter unit VTB and the receiver unit VRB feature a modular structure consisting of a base module or baseboard common to both units and one or more exchangeable adapter cards attached to or inserted into the baseboards to perform selected functions. The basebord is unitary; its components are activated depending upon the baseboard being in a VTB or a VRB. Each card is unique and earmarked and serves a specific purpose, e.g. for video coding and decoding, SMPTE processing, clocking/re-clocking, audio embedding/extraction. Upon inserting a card into a baseboard, the earmark is identified and the baseboard configured as transmitter or receiver baseboard. Functions in the baseboard can be implemented in Field Programmable Gate Arrays (FPGAs) and the network management, configuration, and/or control of the transmitting and/or receiving processes be performed by a softcore processors.

Abstract: The system transmits High Definition (HD) video/audio data, e.g. a JPEG2000-compressed video stream multi-channel audio stream, over a packet switching network, e.g. an Ethernet or IP network. Both the transmitter unit VTB and the receiver unit VRB feature a modular structure consisting of a base module or baseboard common to both units and one or more exchangeable adapter cards attached to or inserted into the baseboards to perform selected functions. The basebord is unitary, i.e. identical for both the VTB and the VRB; its components are activated depending upon the baseboard being in a VTB or a VRB. Each card is unique and earmarked and serves a specific purpose, e.g. for video coding and decoding, SMPTE processing, clocking/re-clocking, audio embedding/extraction. Upon inserting a card into a baseboard, the earmark is identified and the baseboard configured as transmitter or receiver baseboard.

Abstract: The present invention relates to a mobile apparatus comprising an integrated circuit to operate predefined functions, which integrated circuit is susceptible to be set in a standby operating mode wherein which said circuit can resume operation within a predefined delay. The circuit comprises configuration sequential logic having defined states that need to be stored before the circuit enters in standby mode. The mobile apparatus further comprises a power down unit for storing the states of the configuration sequential logic into a low leakage storage area during standby mode that reduces standby current considerably.

Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5), a second bus master (4) linked to the second bus (6), a first and a second communication channel (7, 20, 8, 21) linking the first and the second bus master (3, 4) with each other, and a control unit (9) controlling the data transfer between the first and the second bus master (3, 4) via the first and the second communication channel (7, 20, 8, 21).

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5), a second bus master (4) linked to the second bus (6), a first and a second communication channel (7, 20, 8, 21) linking the first and the second bus master (3, 4) with each other, and a control unit (9) controlling the data transfer between the first and the second bus master (3, 4) via the first and the second communication channel (7, 20, 8, 21).

Abstract: System comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via two bi-directional communication channels for exchanging information. For establishing the bi-directional communication channels, the system comprises a first processor bus (10) to which the first processor (P1) is connected, a first direct memory access unit (45), a first programmable unit (34), and a first shareable unit (13). The programmable unit (34) can be programmed by the first processor (P1). Also comprised is a second processor bus (20), the second processor (P2) being connectable to the second processor bus (20), a second direct memory access unit (35), and a second programmable unit (44). Said second programmable unit (44) is programmable by the second processor (P2).

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.

Abstract: The system and method for emulating a non-volatile memory, in particular a flash memory, embedded in an integrated circuit comprises an integrated circuit with the non-volatile memory, a processor, an interface, a control unit, which controls the embedded non-volatile memory and the interface, and a bus, which connects controllably the interface, the processor and the control unit. The system further comprises an external memory, connected to the interface, in which memory the emulation takes place. The control unit connects the external memory to the bus over the interface or the non-volatile memory to the bus. By using such a design, emulation of a slow embedded (internal) memory is simplified and modifications, e.g. software break points, patches and downloads, can be easily introduced, and processor accesses may be traced.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.

Abstract: Circuit configuration for signal transmission from a finite state machine that can be operated at a first clock rate to a finite state machine that can be operated at a second clock rate, the signal from the transmitting finite state machine being transferable through an asynchronous storage element and a synchronous storage element connected thereto, to the receiving finite state machine which is designed for transmitting a reset signal to the asynchronous storage element after the signal transmission.

Abstract: A system (70) comprising a microprocessor (74), a data bus (75) for writing data into a Flash memory device (71) and a data bus (75) for reading data from the Flash memory device (71). The Flash memory device (71) comprises an error correction encoder (72), a Flash memory (71), an error correction decoder (73), and a Flash data bus (75) for interconnecting the error correction encoder (72), the Flash memory (71), and the error correction decoder (73). The data, when being processed by the error correction encoder (72) are converted into a word that comprises a status word (51), a data word (52), and a redundancy word (53). This approach enables error correction with single-bit alterability.

Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: This invention relates to the structure and design of integrated circuits (ICs), in particular to the embedding or integration of a non-volatile, so-called flash memory into ICs. To solve the issues created by speed differences of the embedded flash memory compared to the other components on an IC, in particular the microprocessor and/or other memory on the IC, a specific writing interface is provided for the flash memory which makes the latter appear like standard memory from a software viewpoint. This writing interface includes a bank of registers (2) between flash memory (7) and microprocessor (6), essentially being operated by a write controller (1) and a flash bus arbiter (8) and acting, in principle, as a intermediate buffering mechanism controlled by a state machine.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.