Abstract: The present invention includes method and apparatus for a device including two capacitors separated by a gap within one package thereby the two capacitors are coupled to each other in such a way that the impedance between them are matched with respect to the other components along a transmission path.

Abstract: The present invention includes method and apparatus for a device including two capacitors separated by a gap within one package thereby the two capacitors are coupled to each other in such a way that the impedance between them are matched with respect to the other components along a transmission path.

Abstract: The invention includes a method and apparatus for enabling multipoint bus access. In one example, the open ring-architecture bus includes a boundary scan bus including a plurality of bus access points adapted for interfacing with a plurality of circuit packs, a first termination circuit coupled to a first end of the bus, and a second termination circuit coupled to a second end of the bus. The first termination circuit and second termination circuit are adapted for terminating signaling on the boundary scan bus. The open-ring architecture bus provides a master circuit pack a multipoint access capability such that the master circuit pack may be disposed at any of the plurality of bus access points. In one example, signaling includes signaling operable for performing hierarchical system testing, including boundary scan testing. In another example, signaling includes upgrade signaling operable for performing firmware upgrades, software upgrades, and like circuit pack upgrades.

Abstract: A power supply particularly suitable for high-speed optical data transmission employs readily available components to achieve desired voltage tolerances. More specifically, a voltage signal supplied to a load is converted into a digital signal and provided to a processor that derives a digital correction signal from the digital signal. The digital correction signal is then converted to an analog correction signal and is used by a feedback control circuit in the power supply to regulate the output voltage.

Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: A power supply particularly suitable for high-speed optical data transmission employs readily available components to achieve desired voltage tolerances. More specifically, a voltage signal supplied to a load is converted into a digital signal and provided to a processor that derives a digital correction signal from the digital signal. The digital correction signal is then converted to an analog correction signal and is used by a feedback control circuit in the power supply to regulate the output voltage.

Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: A phase detector including a voltage controlled oscillator generating a voltage controlled oscillator output, and a first logic state device for receiving said voltage controlled oscillator output as an input. The phase detector also includes a reset device, for generating a reset signal to reset the first logic state device such that the output control signal of the first logic state device reaches a low level in response to a first edge of the reset signal.

Abstract: The present invention relates generally to the field phase detectors and particularly to a phase detector being formed by a flip-flop.