Abstract: The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.

Abstract: The invention relates to a method for producing a transistor with a high degree of electron mobility and to a transistor with a high degree of electron mobility. The method is characterized in that an epitaxial layer is first grown on a flat substrate, and the flat substrate is then completely removed from the bottom of the epitaxial layer, wherein a thermally conductive layer is applied onto the bottom of the epitaxial layer such that the thermally conductive layer contacts at least 80%, preferably at least 90%, particularly preferably at least 95%, in particular 100%, of the bottom of the epitaxial layer. The method is simple and inexpensive to carry out and provides a transistor which has a high degree of electron mobility, an improved electric output without backgating, and an improved heat dissipation. The method additionally allows a transistor to be provided with a vertical transistor structure.

Abstract: This invention concerns a gate structure and a process for its manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thermo-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal). The gate structure according to the invention comprises a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, the intermediate layer-having a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged within the recess, the contact element completely filling the recess and extending to above the intermediate layer, the contact element resting at least in sections directly on the intermediate layer; the contact element being made of a Schottky metal and the contact element having an interior cavity completely enclosed by the Schottky metal.

Abstract: The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to a gate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.

Abstract: This invention concerns a gate structure and a process for manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thereto-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal).

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.

Abstract: An overvoltage protection device for compound semiconductor field effect transistors includes an implanted region disposed in a compound semiconductor material. The implanted region has spatially distributed trap states which cause the implanted region to become electrically conductive at a threshold voltage. A first contact is connected to the implanted region. A second contact spaced apart from the first contact is also connected to the implanted region. The distance between the first and second contacts partly determines the threshold voltage of the overvoltage protection device.

Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: The invention concerns about electrical devices having improved transfer characteristics and a corresponding method of tailoring the transfer characteristics of such electrical devices. According to one aspect of the invention, there is provided an electrical device including at least two transistor segments or at least two transistors connected in parallel or in series characterized in that the at least two segments of the transistor or the at least two of the transistors have a different single transfer characteristic due to at least one of different topology and different material properties.