Abstract: Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.

Abstract: Aspects include computing devices, systems, and methods for managing a first computing device component of a computing device in order to extend an operating life of the computing device component. In an aspect, a processing device may determine a condition estimator of the first computing device component, determine whether the condition estimator of the first computing device component indicates that a condition of the first computing device component is worse than the condition of a second computing device component, and assign workloads to the first and second computing device components to balance deterioration of the condition of the first and second computing device components in response to determining that the condition estimator of the first computing device component indicates that the condition of the first computing device component is worse than the condition of the second computing device component.

Abstract: Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.

Abstract: Aspects include computing devices, systems, and methods for managing a first computing device component of a computing device in order to extend an operating life of the computing device component. In an aspect, a processing device may determine a condition estimator of the first computing device component, determine whether the condition estimator of the first computing device component indicates that a condition of the first computing device component is worse than the condition of a second computing device component, and assign workloads to the first and second computing device components to balance deterioration of the condition of the first and second computing device components in response to determining that the condition estimator of the first computing device component indicates that the condition of the first computing device component is worse than the condition of the second computing device component.

Abstract: Systems and methods for providing local hardware limit management and enforcement are described. One embodiment includes a system for managing and enforcing hardware limits on a system on chip (SoC). The system includes a plurality of chip components provided on a system on chip (SoC). A network of local limit manager (LLM) components is distributed on the SoC. Each LLM component is in communication with a corresponding sensor module that monitors one or more of the chip components. Each LLM component comprises a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module.

Abstract: Systems and methods for providing local hardware limit management and enforcement are described. One embodiment includes a system for managing and enforcing hardware limits on a system on chip (SoC). The system includes a plurality of chip components provided on a system on chip (SoC). A network of local limit manager (LLM) components is distributed on the SoC. Each LLM component is in communication with a corresponding sensor module that monitors one or more of the chip components. Each LLM component comprises a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module.

Abstract: An apparatus includes a transmitter configured to broadcast data to a plurality of receivers is provided. A control circuit is configured to arrange the transmitter to broadcast the data based on a protocol and to arrange the transmitter to broadcast a subset of the data in response to a request from one of the plurality of receivers. In another aspect, a method for operating a broadcast interface is provided. The method includes broadcasting data to a plurality of receivers based on a protocol and broadcasting a subset of the data in response to a request from one of the plurality of receivers. Another apparatus is provided which includes means for broadcasting data to the plurality of receivers based on a protocol and means for arranging the means for broadcasting to broadcast a subset of the data in response to a request from one of the plurality of receivers.

Abstract: Systems and methods for providing local hardware limit management and enforcement are described. One embodiment includes a system for managing and enforcing hardware limits on a system on chip (SoC). The system includes a plurality of chip components provided on a system on chip (SoC). A network of local limit manager (LLM) components is distributed on the SoC. Each LLM component is in communication with a corresponding sensor module that monitors one or more of the chip components. Each LLM component comprises a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module.