Abstract: A sequence of control instructions and a number of insertion instructions are stored in memory element groups of a memory accessed by associated addresses in a stored program controlled telecommunications system. The sequence is read and decoded in response to successive address increments. In order to insert one of the insertion instructions between the control instructions, the sequence includes an insertion step or reference indicating a first address assigned to the insertion instruction and a second address assigned to one of the control instructions. Upon decoding the insertion reference, a logical buffering unit is used in order to replace the successive address incrementing by such address transfers that the control instruction accessed by the second address is decoded subsequent to the insertion instruction which itself is decoded after the insertion reference.

Abstract: Instructions which are read from a program memory of a control computer employing indirect addressing of a data memory are stored temporarily and sequentially in a buffer memory to form an execution queue. The absolute address to the data memory is generated by an address calculator by means of a base address derived from a reference memory in correspondence to an input address and by means of at least one address parameter which has been recorded in a register memory in connection with the execution of an instruction read from the buffer memory and transferred to a parameter register prior to the address calculation. In addition to each instruction, information is recorded in the buffer memory to indicate on the one hand whether the instruction is of the type which performs a write or read operation in the data memory and on the other hand whether it is of the type which enters address parameters in the register memory.

Abstract: Apparatus wherein a sequence of control instructions and a number of insertion instructions are stored in memory element groups of a memory accessed by associated addresses in a stored program controlled telecommunication system. The sequence is read and decoded in response to successive address increments. In order to insert one of the insertion instructions between the control instructions, the sequence includes an insertion step or reference indicating a first address assigned to the insertion instruction and a second address assigned to one of the control instructions. Upon decoding the insertion reference, a logical buffering unit is used in order to replace the successive address incrementing by such address transfers that the control instruction accessed by the second address is decoded subsequent to the insertion instruction which itself is decoded after the insertion reference.

Abstract: The invention relates to an apparatus in a computer system for transmitting signals from one processor to one or several other processors connected to the same bus system so that the signals having priority are transmitted without time delay and that the sequence of signals without priority is not changed. Each processor contains a sender buffer for sending all the signals and a queue buffer for storing signals without priority. If signals having no priority prevent signals having priority from being transmitted through the bus system because of congestion in the receiving equipment, the apparatus allows such signal having no priority to move from the sender buffer to the first place in said queue buffer.