Abstract: A voltage monitor circuit comprises: a monitored voltage input (42); a reference capacitor (32) arranged to be able to store a value of the monitored voltage as a reference capacitor voltage; a timeout capacitor (34) arranged to be able to store a value of the monitored voltage as a timeout capacitor voltage. The timeout capacitor undergoes a higher leakage than the reference capacitor. The voltage monitor circuit also comprises a comparator (2) arranged to: compare the monitored voltage to the reference capacitor voltage; compare the timeout capacitor voltage to the reference capacitor voltage; and produce a logic signal on an output (9) of the comparator based on said comparisons, the logic signal having a first logic value at least if the reference capacitor voltage is lower than or equal to both the monitored voltage and the timeout capacitor voltage.

Abstract: A low-dropout voltage regulator (2) comprises: a differential amplifier portion (4) including a first amplifier input connected to a reference voltage (16), a second amplifier input, and a differential output which is determined by a difference between the reference voltage and a voltage on the second amplifier input; an output portion (10) arranged to provide a regulator output voltage (62) which is controlled by the differential output of the amplifier portion, the second amplifier input being connected to or derived from (70) the regulator output voltage; and a biasing portion (8) arranged to measure an external load current and to provide a biasing current to the differential amplifier portion which depends on the load current.

Abstract: A voltage monitor circuit comprises: a monitored voltage input (42); a reference capacitor (32) arranged to be able to store a value of the monitored voltage as a reference capacitor voltage; a timeout capacitor (34) arranged to be able to store a value of the monitored voltage as a timeout capacitor voltage. The timeout capacitor undergoes a higher leakage than the reference capacitor. The voltage monitor circuit also comprises a comparator (2) arranged to: compare the monitored voltage to the reference capacitor voltage; compare the timeout capacitor voltage to the reference capacitor voltage; and produce a logic signal on an output (9) of the comparator based on said comparisons, the logic signal having a first logic value at least if the reference capacitor voltage is lower than or equal to both the monitored voltage and the timeout capacitor voltage.

Abstract: A low-dropout voltage regulator (2) comprises: a differential amplifier portion (4) including a first amplifier input connected to a reference voltage (16), a second amplifier input, and a differential output which is determined by a difference between the reference voltage and a voltage on the second amplifier input; an output portion (10) arranged to provide a regulator output voltage (62) which is controlled by the differential output of the amplifier portion, the second amplifier input being connected to or derived from (70) the regulator output voltage; and a biasing portion (8) arranged to measure an external load current and to provide a biasing current to the differential amplifier portion which depends on the load current.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.

Abstract: A single bit line reference signal path or line is used for both voltage subtraction and self-timing of a second sense that is longer than a first sense in a dual-sense, single-read memory cell. The self-timing mechanism includes an analog circuit.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.

Abstract: A single bit line reference signal path or line is used for both voltage subtraction and self-timing of a second sense that is longer than a first sense in a dual-sense, single-read memory cell. The self-timing mechanism includes an analog circuit.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.