Abstract: A field-effect structure formed on a substrate and comprising a channel with source and drain as well as a gate that is separated from the channel by an insulating layer. The channel is made of a high T.sub.c metal-oxide superconductor, e.g., YBaCuO, having a carrier density of about 10.sup.21 /cm.sup.3 and a correlation length of about 0.2 nm. The channel thickness is preferrable in the order of 1 nm. The superconductor is preferably a single crystalline and oriented such that the superconducting behavior is strongest in the plane parallel to the substrate. With a signal of a few volts applied to the gate, the entire channel cross-section is depleted of charge carriers whereby the channel resistance can be switched between a "zero resistance" (undepleted, superconducting) state and "very high resistance" (depleted state).

Abstract: A four layer charge storage structure comprising alternate layers of silicon-rich silicon dioxide and silicon dioxide with electrode layers on top and bottom. The upper and middle silicon-rich layers act as enhanced Fowler-Nordheim injectors and the middle silicon-rich layer also stores charges since the silicon particles act as deep traps. The charge storage structure is applicable to nonvolatile memories.

Abstract: A method for the fabrication of self-aligned MESFET structures with a recessed refractory submicron gate. After channel formation on a semi-insulating (SI) substrate, which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing, refractory gate material is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of, e.g., GaAs, using MOCVD of MBE processes resulting in poly-crystalline material over the gate "mask" and mono-crystalline material on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes. In order to further improve process reliability, insulating sidewalls are provided at the vertical edges of the gate to avoid source-gate and drain-gate shorts.

Abstract: The transistor comprises two electrodes, (source (22) and drain (23), with a semiconductor tunnel channel (21A, 21B) arranged therebetween. A gate (24) for applying control signals is coupled to the channel. The semiconductor channel consists of a plurality of regions differing in their current transfer characteristics: contact regions (21c), connected to the source and drain electrodes, and a tunneling region (21t) arranged between the contact regions. The energy of free carriers in the contact regions differs from the energy of the conduction band or the valence band of the tunneling region which forms a low energy tunnel barrier the height (.DELTA.E) of which can be modified by control signals applied to the gate. The operating temperature of the device is kept sufficiently low to have the tunnel current through the barrier outweigh currents of thermionically excited carriers.

Abstract: A matrix addressable liquid crystal display includes a thin film circuit supported on a substrate having a plurality of parallel bit lines. A plurality of individual pixel circuits each include a two terminal bi-directional gate device which is formed from at least one thin film layer with one gate device terminal connected with the associated bit line. A terminal plate is connected in circuit with the other terminal of the gate device. A transparent cover plate is spaced above the thin film circuit with a transparent conductor structure on the underside of the cover plate.The space beneath the cover plate is filled with a liquid crystal display material to form individual display pixel circuits at the terminal plates. A plurality of parallel word lines are arranged orthogonally to, and insulated from, the bit lines. The word lines are connected in circuit with the individual display pixel circuits at the respective cross-overs with the bit lines.