Abstract: A memristive multi-terminal spiking neuron apparatus, comprising a non-volatile memristor, wherein the non-volatile memristor has a resistance ratio between the high-resistance and low-resistance states exceeding 4 decades of magnitude, wherein the non-volatile memristor retains its resistance states for a time period exceeding 1 second, a volatile memristor, wherein the volatile memristor retains its low-resistance state for a time period of less than 10 nanoseconds, and a capacitor, wherein the volatile memristor is in parallel with the capacitor. A method of making a programmable electrical spiking output from a memristive multi-terminal spiking neuron, comprising providing one or more devices wherein each device comprises a non-volatile memristor, a volatile memristor, wherein the volatile memristor is in parallel with the capacitor, providing a first input spiking signal to a neuron device, providing a second input spiking signal, and creating a programmable spiking output signal which changes.

Abstract: A memristive multi-terminal spiking neuron apparatus, comprising a non-volatile memristor, wherein the non-volatile memristor has a resistance ratio between the high-resistance and low-resistance states exceeding 4 decades of magnitude, wherein the non-volatile memristor retains its resistance states for a time period exceeding 1 second, a volatile memristor, wherein the volatile memristor retains its low-resistance state for a time period of less than 10 nanoseconds, and a capacitor, wherein the volatile memristor is in parallel with the capacitor. A method of making a programmable electrical spiking output from a memristive multi-terminal spiking neuron, comprising providing one or more devices wherein each device comprises a non-volatile memristor, a volatile memristor, wherein the volatile memristor is in parallel with the capacitor, providing a first input spiking signal to a neuron device, providing a second input spiking signal, and creating a programmable spiking output signal which changes.

Abstract: According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to divert a portion of current away from the memory cell in response to a voltage at the input line being greater than a threshold voltage.

Abstract: A composite selector electrode includes a switching layer coupled in electrical parallel with a conducting layer. The switching layer is electrically insulating when the temperature of the switching layer is below a threshold temperature. The switching layer exhibits insulator-metal transition at the threshold temperature. The switching layer is electrically conducting when the temperature of the switching layer is above the threshold temperature.

Abstract: Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.

Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.

Abstract: A multiphase selector includes a first electrode, a switching layer coupled to the first electrode, a capping layer coupled to the switching layer, and a second electrode coupled to the capping layer. The switching layer may include a matrix having a first, relatively insulating phase of a transition metal oxide; a second, relatively conducting phase of the transition metal oxide dispersed in the matrix; and a catalyst, located within the matrix, to interact with the first phase of the transition metal oxide to selectively form and position the second phase of the transition metal oxide within the matrix.

Abstract: A resistive memory device includes a bottom electrode and a top electrode crossing the bottom electrode at a non-zero angle. A switching region operatively contacts the bottom electrode and the top electrode. The switching region defines a current path between the bottom electrode and the top electrode in an ON state. An oxygen-supplying layer operatively contacts a portion of the switching region. The oxygen-supplying layer is positioned orthogonally to the current path and to the switching region.

Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

Abstract: A composite selector electrode includes a switching layer coupled in electrical parallel with a conducting layer. The switching layer is electrically insulating when the temperature of the switching layer is below a threshold temperature. The switching layer exhibits insulator-metal transition at the threshold temperature. The switching layer is electrically conducting when the temperature of the switching layer is above the threshold temperature.

Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.

Abstract: A method to program a memristive device includes applying a pulse sequence including at least a series of pulses in alternating polarity to set the memristive device. The series has an odd number of pulses where odd numbered pulses have a first electrical polarity that switches the device to the state and even numbered pulse or pulses have a second electrical polarity.

Abstract: According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to divert a portion of current away from the memory cell in response to a voltage at the input line being greater than a threshold voltage.

Abstract: A multiphase selector includes a first electrode, a switching layer coupled to the first electrode, a capping layer coupled to the switching layer, and a second electrode coupled to the capping layer. The switching layer may include a matrix having a first, relatively insulating phase of a transition metal oxide; a second, relatively conducting phase of the transition metal oxide dispersed in the matrix; and a catalyst, located within the matrix, to interact with the first phase of the transition metal oxide to selectively form and position the second phase of the transition metal oxide within the matrix.

Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

Abstract: A resistive memory device includes a bottom electrode and a top electrode crossing the bottom electrode at a non-zero angle. A switching region operatively contacts the bottom electrode and the top electrode. The switching region defines a current path between the bottom electrode and the top electrode in an ON state. An oxygen-supplying layer operatively contacts a portion of the switching region. The oxygen-supplying layer is positioned orthogonally to the current path and to the switching region.

Abstract: Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area.

Abstract: A method to program a memristive device includes applying a pulse sequence including at least a series of pulses in alternating polarity to set the memristive device. The series has an odd number of pulses where odd numbered pulses have a first electrical polarity that switches the device to the state and even numbered pulse or pulses have a second electrical polarity.

Abstract: Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.

Abstract: A varied multilayer memristive device includes a first memristive device stacked on a second memristive device. The physical parameters of the second memristive device differ from physical parameters of the first memristive to account for thermal budgeting differences present during formation processes for the memristive devices to reach specified performance parameters.