Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: A signature graph method is proposed to authenticate shared high-entropy data using a graph that can be easily identified by human eyes (or by computer image recognition algorithms). An example method for authenticating a shared data element comprises receiving a data element to be shared; transforming the data element to be shared into signature graph data, using at least one collision-resistant one-way mapping function; and rendering a human-perceptible representation of the signature graph data, such as an audible and/or visual representation, for perception by a human user. In some embodiments, transforming the data element comprises applying a cryptographic hash function to the data element, to obtain a first hash output, and applying a cryptographic hash function to the first hash output, to obtain the signature graph data.

Abstract: A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.

Abstract: In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Abstract: Systems, apparatus, and methods measure a signal provided by a capacitance sensor, the signal indicative of a presence of an object proximate to the capacitance sensor. Responsive to measuring the signal, embodiments access control information in a memory to determine whether the signal is associated with a first qualifying event of the control information. Responsive to determining that the signal is associated with the first qualifying event, embodiments control a power consumption of a communication device.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells: a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. Caches in XIP interfaces provide seamless access to multiple memories, or multiple portions of a single memory. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.

Abstract: Systems, apparatus, and methods measure a signal provided by a capacitance sensor, the signal indicative of a presence of an object proximate to the capacitance sensor. Responsive to measuring the signal, embodiments access control information in a memory to determine whether the signal is associated with a first qualifying event of the control information. Responsive to determining that the signal is associated with the first qualifying event, embodiments control a power consumption of a communication device.