Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (?1) to a first input voltage (±Vm) and on a second clock signal (?2) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negative r

Abstract: A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.

Abstract: A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.

Abstract: Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.