Abstract: A resonant magnetic coupling wireless power transfer system with calibration capabilities of the resonant frequencies of its power transmitter(s) and power receiver(s) is disclosed. The system detects the peak voltages of the coil inductors or the resonant capacitors and tunes the resonant capacitors until the detected peak voltages reach their maximal values given proper setup conditions, so as to calibrate the inductor-capacitor (LC) resonance frequencies of the power transmitter(s) and the power receiver(s) in the resonant magnetic coupling wireless power transfer system to achieve the highest power transferred to the load and a high PTE.

Abstract: A resonant magnetic coupling wireless power transfer system with calibration capabilities of the resonant frequencies of its power transmitter(s) and power receiver(s) is disclosed. The system detects the peak voltages of the coil inductors or the resonant capacitors and tunes the resonant capacitors until the detected peak voltages reach their maximal values given proper setup conditions, so as to calibrate the inductor-capacitor (LC) resonance frequencies of the power transmitter(s) and the power receiver(s) in the resonant magnetic coupling wireless power transfer system to achieve the highest power transferred to the load and a high PTE.

Abstract: A novel quadrature phase-shift keying (QPSK) demodulator, called the bowknot quadrature phase-shift keying (BQPSK) demodulator, is disclosed. The BQPSK demodulator uses a delay circuit to delay a BQPSK signal and mixes the delayed BQPSK signal with the undelayed BQPSK signal to output an I-channel data signal and a Q-channel data signal. The BQPSK demodulator further uses a phase rotation circuit to demodulate the orthogonal data signals and obtain a recovery clock signal. The BQPSK demodulator neither uses an A/D converter nor uses a quadrature oscillator, featuring high data rate, low power consumption, simple architecture and superior reliability. The BQPSK demodulator can be realized by digital circuits and analog circuits.

Abstract: A novel quadrature phase-shift keying (QPSK) demodulator, called the bowknot quadrature phase-shift keying (BQPSK) demodulator, is disclosed. The BQPSK demodulator uses a delay circuit to delay a BQPSK signal and mixes the delayed BQPSK signal with the undelayed BQPSK signal to output an I-channel data signal and a Q-channel data signal. The BQPSK demodulator further uses a phase rotation circuit to demodulate the orthogonal data signals and obtain a recovery clock signal. The BQPSK demodulator neither uses an A/D converter nor uses a quadrature oscillator, featuring high data rate, low power consumption, simple architecture and superior reliability. The BQPSK demodulator can be realized by digital circuits and analog circuits.

Abstract: The present invention discloses BPSK demodulator, which uses a delay circuit to delay a BPSK signal and mixes the delayed BPSK signal with the undelayed BPSK signal to output a demodulated data signal, and which uses a phase rotation circuit and the demodulated data signal to obtain a carrier clock signal. The operating frequency of the delay circuit is the same as or 0.5 times the carrier frequency. Therefore, the present invention consumes less power and is realized by digital circuits and analog circuits.

Abstract: A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.

Abstract: A successive approximation (SA) analog-to-digital converter (ADC) capable of estimating its own capacitance weight errors includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

Abstract: A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.

Abstract: The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory.

Abstract: The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory.

Abstract: A method for estimating capacitance weight errors of a digital-to-analog converter and a successive approximation (SA) analog-to-digital converter (ADC) using the same are disclosed, and the SA ADC includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

Abstract: A device capable of receiving one or more digital stimulus signals and accurately measuring an open-loop gain of an amplifier comprises: a digital charge converter (DCC), a charge integrator, an A/D converter, a control logic circuit and an arithmetic logic unit (ALU). The DCC and the charge integrator are composed of a plurality of switches, one or more sampling capacitor, at least one integrating capacitor and an operational amplifier under test (OPAUT) with a single-ended output or differential-ended outputs. The DCC, the charge integrator, and the A/D converter are controlled by control signals generated by the logic control circuit and can be reconfigured as a first-order Sigma-Delta modulator capable of receiving at least one of the digital input stimulus signals. The ALU calculates the open-loop gain of the OPAUT with single-ended output or differential-ended outputs according to the digital stimulus signals and the digital output of the first-order Sigma-Delta modulator.

Abstract: A device capable of receiving one or more digital stimulus signals and accurately measuring an open-loop gain of an amplifier comprises: a digital charge converter (DCC), a charge integrator, an A/D converter, a control logic circuit and an arithmetic logic unit (ALU). The DCC and the charge integrator are composed of a plurality of switches, one or more sampling capacitor, at least one integrating capacitor and an operational amplifier under test (OPAUT) with a single-ended output or differential-ended outputs. The DCC, the charge integrator, and the A/D converter are controlled by control signals generated by the logic control circuit and can be reconfigured as a first-order Sigma-Delta modulator capable of receiving at least one of the digital input stimulus signals. The ALU calculates the open-loop gain of the OPAUT with single-ended output or differential-ended outputs according to the digital stimulus signals and the digital output of the first-order Sigma-Delta modulator.

Abstract: A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests disclosed in the present invention provides the digital input interfaces, which are comprised of capacitors, analog switches and digital circuits, for the usage of testing the mixed-signal circuits. The present invention provides a low-priced testing platform to accomplish the testing of circuits and to solve the problems of high-cost mixed mode tester and of utmost restrictions against the surrounding condition. Therefore, the present invention improves the testability, reduces the test cost, shorten the processes of designation and efficiently seize on the time-to-market.

Abstract: A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests disclosed in the present invention provides the digital input interfaces, which are comprised of capacitors, analog switches and digital circuits, for the usage of testing the mixed-signal circuits. The present invention provides a low-priced testing platform to accomplish the testing of circuits and to solve the problems of high-cost mixed mode tester and of utmost restrictions against the surrounding condition. Therefore, the present invention improves the testability, reduces the test cost, shorten the processes of designation and efficiently seize on the time-to-market.

Abstract: A bandgap voltage reference generator includes a bandgap voltage reference circuit and a fast startup circuit. The fast start-up circuit, which is cost-efficient and saves power consumption, can rapidly start up the bandgap reference voltage circuit coupled thereto. The fast start-up circuit comprises a P-channel MOSFET or an N-channel MOSFET. Upon the bandgap voltage reference generator being powered by an external DC voltage, the bandgap reference generator will possibly operate in the power-down operating state. At this time there exists a large voltage drop between the gate and the source of the P-channel MOSFET (or N-channel MOSFET), and thus a large current flows rapidly through the P-channel MOSFET (or N-channel MOSFET). Voltages of drains of two specific MOSFETs in the bandgap voltage reference circuit will thus be pulled to be substantially the same, and the bandgap voltage reference circuit is brought into a normal operating state.

Abstract: A bandgap voltage reference generator includes a bandgap voltage reference circuit and a fast startup circuit. The fast start-up circuit, which is cost-efficient and saves power consumption can rapidly start up the bandgap reference voltage circuit coupled thereto. The fast start-up circuit comprises a P-channel MOSFET or an N-channel MOSFET. Upon the bandgap voltage reference generator is powered by an external DC voltage, the bandgap reference generator will possibly operates in power-down operating state. At the time, there exists a large voltage drop between the gate and the source of the P-channel MOSFET (or N-channel MOSFET), and thus a large current flows rapidly through the P-channel MOSFET (or N-channel MOSFET). Voltages of drains of two specific MOSFETs in the bandgap voltage reference circuit will thus be pulled to be substantially the same, and the bandgap voltage reference circuit is brought into normal operating state.