Patents by Inventor Hao-Hsuan Chiu

Hao-Hsuan Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941157
    Abstract: A computer implemented method for managing the scope of permissions granted by users to application that includes collecting a set of permissions for an application from an application provider publication; and collecting a process flow for functional steps of the application from a review of the application that is published on a product review type publication. The computer implemented method further includes dividing the functional steps of the application into a plurality of journeys, each of said plurality of journeys having a function associated with a stage of a functional step from a perspective of a user; and matching permissions from the set of permissions for each journey of said plurality of journeys to provide matched permissible permissions to journeys stored in a customer journey store.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 26, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hao Chun Hung, Po-Cheng Chiu, Tsai-Hsuan Hsieh, Cheng-Lun Yang, Chiwen Chang, Shin Yu Wey
  • Patent number: 11914491
    Abstract: A USB integrated circuit (IC), a testing platform and an operating method for USB integrated circuit are provided. The USB integrated circuit includes a USB port physical layer (PHY) circuit, a first lane adapter, a second lane adapter, a routing circuit, and a USB transport layer circuit. The USB PHY circuit is configured to transmit a differential signal between the USB integrated circuit and an outside device. When the USB integrated circuit operates in a testing mode, the routing circuit electrically connects the first lane adapter to the USB PHY circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second lane adapter to the USB PHY circuit. The USB transport layer circuit is coupled to the first lane adapter and the second lane adapter.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: February 27, 2024
    Assignee: VIA LABS, INC.
    Inventor: Hao-Hsuan Chiu
  • Publication number: 20230176954
    Abstract: A USB integrated circuit (IC), a testing platform and an operating method for USB integrated circuit are provided. The USB integrated circuit includes a USB port physical layer (PHY) circuit, a first lane adapter, a second lane adapter, a routing circuit, and a USB transport layer circuit. The USB PHY circuit is configured to transmit a differential signal between the USB integrated circuit and an outside device. When the USB integrated circuit operates in a testing mode, the routing circuit electrically connects the first lane adapter to the USB PHY circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second lane adapter to the USB PHY circuit. The USB transport layer circuit is coupled to the first lane adapter and the second lane adapter.
    Type: Application
    Filed: November 14, 2022
    Publication date: June 8, 2023
    Applicant: VIA LABS, INC.
    Inventor: Hao-Hsuan Chiu
  • Patent number: 10153759
    Abstract: A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 11, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Hao-Hsuan Chiu, Yen-Ting Lai
  • Publication number: 20170005648
    Abstract: A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 5, 2017
    Inventors: Hao-Hsuan CHIU, Yen-Ting LAI
  • Publication number: 20160253273
    Abstract: A hub including an up-stream port, at least one down-stream port, a state-determining unit, and a control unit is provided. The up-stream port is configured to be coupled to a host device. The down-stream port is configured to be coupled to at least one peripheral device. The state-determining unit is coupled to the down-stream port and generates a determination result according to a level of a pin of the down-stream port. The control unit is coupled between the up-stream port and the state-determining unit. When the host device sends a sleep request, the control unit determines whether the peripheral device is operating in a specific mode according to the determination result. When the peripheral device is operating in the specific mode, the control unit provides an unready response to the host device.
    Type: Application
    Filed: April 30, 2015
    Publication date: September 1, 2016
    Inventors: Po-Chou LIN, Hao-Hsuan CHIU
  • Patent number: 9111049
    Abstract: An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: August 18, 2015
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Yi-Lin Lai, Hao-Hsuan Chiu, Terrance Shih
  • Patent number: 8954626
    Abstract: A transmission system receiving a first token packet and a second token packet is disclosed. The transmission system is coupled to a first peripheral device and a second peripheral device. The transmission system includes an upstream port to receive the first and the second token packets. A first transmission path occurs between the upstream port and the first peripheral device. A second transmission path occurs between the upstream port and the second peripheral device. The transmission system analyzes the first and the second token packets. The first token packet includes information corresponding to the first peripheral device. When the second token packet includes information corresponding to the first peripheral device, the transmission system disables the second transmission path.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: February 10, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Hsien-Po Huang, Hao-Hsuan Chiu
  • Patent number: 8842983
    Abstract: A data transmission system and method are provided. The data transmission system includes a first link partner and an optical transceiver unit. The first link partner includes a controller. When the first link partner is in an abnormal operation mode, the controller controls the first link partner to exit from the abnormal operation mode. The optical transceiver unit is coupled between the first link partner and a second link partner and performs data transmission between the first link partner and the second link partner. According to the data transmission system and method, one link partner can accurately detect whether another link partner is coupled to the one link partner through an optical transceiver unit. Accordingly, data transmission between the two link partners can be stably performed through the optical transceiver unit.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: September 23, 2014
    Assignee: Via Technologies, Inc.
    Inventors: Jinkuan Tang, Jiin Lai, Hao-Hsuan Chiu
  • Patent number: 8819301
    Abstract: An apparatus is provided for charging a Universal Serial Bus (USB) device according to an optimal charging mode. The apparatus includes a charging module that is configured to obtain a descriptor from the USB device upon detection of the USB device on a USB bus. The charging module includes one or more descriptor entries disposed in a memory and a controller. The one or more descriptor entries include descriptor data, for matching the descriptor to a specific descriptor entry, and charging data, that specifies the optimal charging mode for the USB device. The controller is coupled to the memory, and is configured to match the descriptor to the specific descriptor entry, and is configured to initiate the optimal charging mode on the USB bus according to the charging data.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: August 26, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Hao-Hsuan Chiu, Terrance Shih
  • Publication number: 20130013819
    Abstract: A transmission system receiving a first token packet and a second token packet is disclosed. The transmission system is coupled to a first peripheral device and a second peripheral device. The transmission system includes an upstream port to receive the first and the second token packets. A first transmission path occurs between the upstream port and the first peripheral device. A second transmission path occurs between the upstream port and the second peripheral device. The transmission system analyzes the first and the second token packets. The first token packet includes information corresponding to the first peripheral device. When the second token packet includes information corresponding to the first peripheral device, the transmission system disables the second transmission path.
    Type: Application
    Filed: February 2, 2012
    Publication date: January 10, 2013
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Hsien-Po HUANG, Hao-Hsuan CHIU
  • Publication number: 20120008938
    Abstract: A data transmission system and method are provided. The data transmission system includes a first link partner and an optical transceiver unit. The first link partner includes a controller. When the first link partner is in an abnormal operation mode, the controller controls the first link partner to exit from the abnormal operation mode. The optical transceiver unit is coupled between the first link partner and a second link partner and performs data transmission between the first link partner and the second link partner. According to the data transmission system and method, one link partner can accurately detect whether another link partner is coupled to the one link partner through an optical transceiver unit. Accordingly, data transmission between the two link partners can be stably performed through the optical transceiver unit.
    Type: Application
    Filed: November 5, 2010
    Publication date: January 12, 2012
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Jinkuan Tang, Jiin Lai, Hao-Hsuan Chiu
  • Publication number: 20070061657
    Abstract: A delay fault testing apparatus includes a scan device having a first input for receiving a data to the core under test, an update device including an input electrically connected to a first output of the scan device, a first multiplexer including a first input electrically connected to the output of the scan device, a second input electrically connected to a first output of the update device, and an output electrically connected to an input of the core under test. The first input of the first multiplexer is switched to the output when a first control signal is asserted so that the output of the scan device is allowed to directly connect to the output of the first multiplexer to launch a transition by switching the first multiplexer rather than triggering an update event, which is restricted to be triggered in the time of a negative edge.
    Type: Application
    Filed: August 12, 2005
    Publication date: March 15, 2007
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tsin-Yuan Chang, Po-Lin Chen, Hao-Hsuan Chiu