Patents by Inventor Hao-Ju Fang

Hao-Ju Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527472
    Abstract: A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: December 13, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cho-Hsin Chang, Hao-Ju Fang, Ting-Wei Chi, Te-Fang Chu
  • Publication number: 20210305148
    Abstract: A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer.
    Type: Application
    Filed: May 6, 2020
    Publication date: September 30, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cho-Hsin Chang, Hao-Ju Fang, Ting-Wei Chi, Te-Fang Chu
  • Patent number: 10074613
    Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: September 11, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Hao-Ju Fang, Hsin-Lung Chung, Cho-Hsin Chang, Tsung-Hsien Tsai, Chia-Yang Chen, Chun-Chi Ke
  • Publication number: 20170236787
    Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Chih-Hsien Chiu, Hao-Ju Fang, Hsin-Lung Chung, Cho-Hsin Chang, Tsung-Hsien Tsai, Chia-Yang Chen, Chun-Chi Ke
  • Patent number: 9673151
    Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 6, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Hao-Ju Fang, Hsin-Lung Chung, Cho-Hsin Chang, Tsung-Hsien Tsai, Chia-Yang Chen, Chun-Chi Ke
  • Patent number: 9526171
    Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: December 20, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Hao-Ju Fang, Kuang-Neng Chung
  • Patent number: 9502758
    Abstract: An electronic package is disclosed, which includes: a substrate; at least an electronic element disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic element; and an antenna body embedded in the encapsulant without contacting with the substrate and exposed from a surface of the encapsulant. Since the antenna body is not disposed on the substrate, the surface area of the substrate can be reduced to meet the miniaturization requirement of the electronic package.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 22, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hsin-Lung Chung, Hao-Ju Fang, Chih-Hsien Chiu, Yude Chu, Tsung-Hsien Tsai
  • Publication number: 20160093576
    Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 31, 2016
    Inventors: Chih-Hsien Chiu, Hao-Ju Fang, Hsin-Lung Chung, Cho-Hsin Chang, Tsung-Hsien Tsai, Chia-Yang Chen, Chun-Chi Ke
  • Publication number: 20150366085
    Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.
    Type: Application
    Filed: December 9, 2014
    Publication date: December 17, 2015
    Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Hao-Ju Fang, Kuang-Neng Chung
  • Publication number: 20150145747
    Abstract: An electronic package is disclosed, which includes: a substrate; at least an electronic element disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic element; and an antenna body embedded in the encapsulant without contacting with the substrate and exposed from a surface of the encapsulant. Since the antenna body is not disposed on the substrate, the surface area of the substrate can be reduced to meet the miniaturization requirement of the electronic package.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 28, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Hsin-Lung Chung, Hao-Ju Fang, Chih-Hsien Chiu, Yude Chu, Tsung-Hsien Tsai
  • Patent number: 8766416
    Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tsung-Hsien Hsu, Hao-Ju Fang, Hsin-Lung Chung
  • Publication number: 20130234337
    Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.
    Type: Application
    Filed: April 27, 2012
    Publication date: September 12, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Tsung-Hsien Hsu, Hao-Ju Fang, Hsin-Lung Chung
  • Publication number: 20120235259
    Abstract: A semiconductor package and a method of fabricating the same. The semiconductor package includes: a substrate having a plurality of semiconductor components disposed thereon; an encapsulant covering the substrate and the semiconductor components; and a metal layer formed on the exposed surfaces of the encapsulant, wherein the encapsulant is formed with a trench for dividing into a plurality of package units on the substrate to allow each of the package units to have at least one of the semiconductor components, and the metal layer is formed in the trench to encompass the encapsulant on the periphery of the semiconductor components, thereby preventing interference of electromagnetic waves between the semiconductor components.
    Type: Application
    Filed: September 23, 2011
    Publication date: September 20, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hao-Ju Fang, Hsin-Lung Chung, Cho-Hsin Chang, Tsung-Hsien Tsai
  • Publication number: 20120170162
    Abstract: A semiconductor package is provided, which includes a substrate unit having conductive pads and ESD protection pads formed on a bottom surface thereof; an encapsulant covering a top surface of the substrate unit; and a metal layer disposed on a top surface of the encapsulant and having connecting extensions formed on side surfaces of the substrate unit and the encapsulant for electrically connecting the ESD protection pads, wherein portions of the side surfaces of the substrate unit corresponding in position to the conductive pads are exposed from the metal layer so as to ensure that solder bumps subsequently formed to connect the conductive pads of the semiconductor package to a circuit board are not in contact with the metal layer, thereby effectively avoiding the risk of short circuits.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 5, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hao-Ju Fang, Hsin-Lung Chung, Kuang-Neng Chung, Chien-Cheng Lin, Heng-Cheng Chu
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee