Patents by Inventor Hao-Juin Liu

Hao-Juin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11088102
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Patent number: 10867810
    Abstract: A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Patent number: 10748785
    Abstract: A device includes a plurality of first pads in a package substrate, wherein at least one first pad is of a first elongated shape, a plurality of vias in a dielectric layer and over the plurality of first pads, and a plurality of second pads over the package substrate, wherein at least one second pad is of a second elongated shape, and wherein the plurality of second pads is over a top surface of the dielectric layer and placed in a first region, a second region, a third region and a fourth region, and wherein second pads in two contiguous regions are oriented in two different directions.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Publication number: 20200098714
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Application
    Filed: November 4, 2019
    Publication date: March 26, 2020
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Publication number: 20200013710
    Abstract: A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 9, 2020
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Patent number: 10468366
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Patent number: 10037973
    Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
  • Patent number: 9978656
    Abstract: The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Han-Ping Pu, Ming-Da Cheng, Chang-Chia Huang, Hao-Juin Liu
  • Publication number: 20170345677
    Abstract: A device includes a plurality of first pads in a package substrate, wherein at least one first pad is of a first elongated shape, a plurality of vias in a dielectric layer and over the plurality of first pads, and a plurality of second pads over the package substrate, wherein at least one second pad is of a second elongated shape, and wherein the plurality of second pads is over a top surface of the dielectric layer and placed in a first region, a second region, a third region and a fourth region, and wherein second pads in two contiguous regions are oriented in two different directions.
    Type: Application
    Filed: August 17, 2017
    Publication date: November 30, 2017
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Publication number: 20170271291
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Patent number: 9741589
    Abstract: A structure comprises a plurality of top pads protruding over a top surface of a package substrate, wherein a top pad comprises a first half-circle portion, a second half-circle portion and a first rectangular portion between the first half-circle portion and the second half-circle portion, a plurality of bottom pads embedded in the package substrate, wherein a bottom pad comprises a third half-circle portion, a fourth half-circle portion and a second rectangular portion between the third half-circle portion and the fourth half-circle portion and a plurality of vias coupled between the top pads and their respective bottom pads.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Patent number: 9673125
    Abstract: A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang, Yu-Jen Tseng, Chen-Shien Chen
  • Patent number: 9673161
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Publication number: 20160336298
    Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 17, 2016
    Inventors: HUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG
  • Publication number: 20160329293
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Patent number: 9472521
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Hao-Juin Liu, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 9406629
    Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
  • Patent number: 9397059
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Publication number: 20160155733
    Abstract: A method comprises depositing a protection layer over a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao-Juin Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20160111384
    Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: HUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG