Abstract: A glucocerebroside compound, a pharmaceutical composition thereof, and the use of the glucocerebroside compound and the pharmaceutical composition thereof in the preparation of drugs for preventing or treating immune-related diseases.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.

Abstract: Provided herein are systems and methods for enhancement of polyphenols, such as chlorogenic acids, chicoric acid, anthocyanins, and water-soluble quercetin derivatives, production in red lettuces. Also provided are transgenic lettuce for the production of polyphenols. Also provided are parts of such transgenic lettuces, such as seeds leaves, and extracts. The disclosure also provides methods of using the new lettuces and parts thereof for protection against viral/bacterial infection (i.e., by inhibiting activities of COVID-19 virus/enzymes) diabetes, cardiovascular diseases, memory and eyesight loss, inflammation, and cancer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: Implementations of this specification provide methods and apparatuses for replaying logs. One method includes: classifying a plurality of logs to be replayed into log queues, sending the log queues to a global replay queue, allocating one or more replay threads to the log queues based on rankings of the log queues in the global replay queue, wherein the one or more replay threads are configured to replay one or more current log queues of the log queues, and in response to identifying an error of a current log queue of the one or more current log queues in a replay process, allocating a replay thread of the one or more replay threads allocated to the current log queue to a log queue that immediately follows the current log queue in the global replay queue.

Abstract: A tunnel oxide layer, an N-type bifacial crystalline silicon solar cell and a method for manufacturing the same are provided. The method for manufacturing the tunnel oxide layer includes forming excess -OH on a back side of a silicon wafer, and depositing the tunnel oxide layer on the back side of the silicon wafer by a Plasma Enhanced Atomic Layer Deposition method. The method for manufacturing the N-type bifacial crystalline silicon solar cell can include following steps: performing cleaning, texturing, boron diffusing, and alkaline polishing on an N-type silicon wafer, sequentially forming a P-type doped layer, a passivation layer, and an anti-reflection layer on a front side of the alkaline-polished N-type silicon wafer, and forming a tunnel oxide layer on a back side of the alkaline-polished N-type silicon wafer, followed by forming an N-type doped polysilicon layer, and after annealing, forming an anti-reflection layer.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A chip-level software and hardware cooperative relay protection device is provided. The device includes: a control chip, wherein a first control unit, a second control unit, and multiple logic circuits are integrated on the control chip; and the logic circuits perform microsecond-level rapid calculation on electrical signals of a protected electrical device, obtain fault feature parameters of the protected electrical device are and transmit same to the first control unit, then perform millisecond-level real-time protection logic determination according to the fault feature parameters of the protected electrical device to obtain relay protection results of the protected electrical device, and protect the protected electrical device by controlling an external relay according to the relay protection results.

Abstract: Embodiments of this application disclose a backup power supply method and a related device. The method includes: calculating a battery capacity of a battery based on historical power outage alarm information and historical power consumption information of a station in which the battery is located; if a power outage occurs in the station, calculating a state of charge of the battery based on actual power consumption and power outage duration of the station, and the battery capacity; and sending a current target energy saving level of the battery to the station if it is determined, based on the state of charge, that an energy saving level of the battery changes, so that the station uses a power saving policy corresponding to the target energy saving level.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: A chip-level software and hardware cooperative relay protection device is provided. The device includes: a control chip, wherein a first control unit, a second control unit, and multiple logic circuits are integrated on the control chip; and the logic circuits perform microsecond-level rapid calculation on electrical signals of a protected electrical device, obtain fault feature parameters of the protected electrical device are and transmit same to the first control unit, then perform millisecond-level real-time protection logic determination according to the fault feature parameters of the protected electrical device to obtain relay protection results of the protected electrical device, and protect the protected electrical device by controlling an external relay according to the relay protection results.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: Embodiments of synchronized hinges for foldable displays are described. In some embodiments, a hinge may include: a first bracket coupled to a first shaft via a first arm, a second bracket coupled to a second shaft via a second arm, and a synchronization bracket coupled to the first and second shafts.

Abstract: An antenna structure includes a first substrate and a second substrate. The first substrate includes: a semiconductor chip configured to transmit or receive a first radio-frequency (RF) signal; a first ground layer configured to provide ground to the semiconductor chip; and a signal layer arranged on a side of the first substrate opposite to the semiconductor chip and configured to transmit the first RF signal. The second substrate has an antenna array formed of antenna cells, each of the antenna cells including: a first antenna layer configured to radiate second RF signals based on the first RF signal; a second ground layer configured to provide ground to the first antenna layer. The antenna device further includes a plurality of connectors electrically coupling the semiconductor chip to the antenna array.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The present invention provides a chip including a plurality of application circuits and a UART interface. The plurality of application circuits, configured to generate a plurality of data, respectively, wherein the plurality of data respectively generated by the plurality of application circuits are transmitted to another chip via the same UART interface.

Abstract: Provided is a two-stage self-organizing optimized aggregation method and system for distributed resources of a virtual power plant.

Abstract: The present invention provides a multiplex PCR detection kit of Listeria monocytogenes serotype 4h. The kit includes a gene Imo1210 detection primer and a gene xysn_1693 detection primer. The present invention establishes a multiplex PCR method for rapidly detecting Listeria monocytogenes serotype 4h by using two pairs of primers.