Patents by Inventor Hao-Yu Tung

Hao-Yu Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interposer routing structure and semiconductor package
    Patent number: 11869846
    Abstract: An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: January 9, 2024
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Fan Yang, Hao-Yu Tung, Hung-Yi Chang, Wei-Chiao Wang, Yi-Tzeng Lin
  • Routing structure between dies and method for arranging routing between dies
    Patent number: 11600572
    Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: March 7, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Liao, Hao-Yu Tung, Yu-Cheng Sun, Ming-Hsuan Wang, Igor Elkanovich
  • ROUTING STRUCTURE BETWEEN DIES AND METHOD FOR ARRANGING ROUTING BETWEEN DIES
    Publication number: 20220293526
    Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Liao, Hao-Yu Tung, Yu-Cheng Sun, Ming-Hsuan Wang, Igor Elkanovich