Patents by Inventor Haobo CHEN
Haobo CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162157Abstract: A bumpless hybrid organic glass interposer. One or more high density pattern (HDP) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. The HDP layer(s) is/are then attached to the substrate package. The interposers achieve electrical connections between the HDP layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the HDP routing.Type: ApplicationFiled: November 16, 2022Publication date: May 16, 2024Applicant: Intel CorporationInventors: Jeremy D. Ecton, Brandon Christian Marin, Aleksandar Aleksov, Srinivas V. Pietambaram, Haobo Chen
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Publication number: 20240128181Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Hiroki Tanaka, Haobo Chen
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Publication number: 20240114622Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Cary Kuliasha, Siddharth K. Alur, Jung Kyu Han, Beomseok Choi, Russell K. Mortensen, Andrew Collins, Haobo Chen, Brandon C. Marin
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Publication number: 20240113158Abstract: Disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. The substrates may include an anode material, a cathode material, and a conductive material. The anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. The cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. The conductive material may be located at the anode peaks.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Jeremy D. Ecton, Brandon C. Marin, Haobo Chen, Changhua Liu, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20240112971Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
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Publication number: 20240105571Abstract: Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: Brandon C. MARIN, Haobo CHEN, Bai NIE, Srinivas V. PIETAMBARAM, Gang DUAN, Jeremy D. ECTON, Suddhasattwa NAD
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Publication number: 20240105576Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core and a pad over the core. In an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. In an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Inventors: Kyle MCELHINNY, Xiaoying GUO, Hiroki TANAKA, Haobo CHEN
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Publication number: 20240105575Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Inventors: Jason M. GAMBA, Haifa HARIRI, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Hiroki TANAKA, Kyle MCELHINNY, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Haobo CHEN, Bai NIE, Numair AHMED
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Publication number: 20240088052Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
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Patent number: 11923312Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: GrantFiled: March 27, 2019Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
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Publication number: 20240071848Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Bohan SHAN, Haobo CHEN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Bai NIE, Gang DUAN, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying David XU, Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD
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Publication number: 20240006283Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Suddhasattawa NAD, Rahul N. MANEPALLI, Gang DUAN, Srinivas V. PIETAMBARAM, Yi YANG, Marcel WALL, Darko GRUJICIC, Haobo CHEN, Aaron GARELICK
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Publication number: 20240006298Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Suddhasattwa Nad, Steve Cho, Marcel Arlan Wall, Onur Ozkan, Ali Lehaf, Yi Yang, Jason Scott Steill, Gang Duan, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Haifa Hariri, Bai Nie, Hiroki Tanaka, Kyle Mcelhinny, Jason Gamba, Venkata Rajesh Saranam, Kristof Darmawikarta, Haobo Chen
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Publication number: 20240006284Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Kristof Darmawikarta, Srinivas Pietambaram, Benjamin Duong, Haobo Chen
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Patent number: 11837534Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.Type: GrantFiled: December 29, 2017Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Kristof Darmawikarta, Haobo Chen, Changhua Liu, Sri Ranga Sai Boyapati, Bai Nie
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Publication number: 20230387027Abstract: A via structure for an embedded component and method for making same. The via structure includes a pillar of conductive material perpendicularly attached to a surface of a build-up dielectric layer. The surface and the pillar are conformally covered by a film layer. The film layer is conformally applied and retains a feature landscape profile. A dielectric layer is located on the film layer, the dielectric layer has an upper dielectric surface that is planar. The pillar has a top that is exposed at the upper dielectric surface.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: Intel CorporationInventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Haobo Chen
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Publication number: 20230197661Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a first material layer on the first surface of the first die, the first material layer including silicon and nitrogen; a second material layer on the first material layer, the second material layer including a photoimageable dielectric; conductive vias through the first and second material layers, wherein respective ones of the conductive vias are electrically coupled to respective ones of the second conductive contacts on the first die; and a second die in a second layer, wherein the second layer on the first layer, and wherein the second die is electrically coupled to the second conductive contacts on the first die by the conductive vias.Type: ApplicationFiled: December 18, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Bai Nie, Haobo Chen, Jason M. Gamba
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Publication number: 20230197679Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Jeremy Ecton, Jason M. Gamba, Brandon C. Marin, Srinivas V. Pietambaram, Xiaoxuan Sun, Omkar G. Karhade, Xavier Francois Brun, Yonggang Li, Suddhasattwa Nad, Bohan Shan, Haobo Chen, Gang Duan
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Patent number: D1012591Type: GrantFiled: October 28, 2022Date of Patent: January 30, 2024Inventors: Jianping Xiao, Haobo Chen, Luping Chen
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Patent number: D1021278Type: GrantFiled: October 9, 2023Date of Patent: April 2, 2024Assignee: Shenzhen Qianhai Runway Technology Co., LTD.Inventors: Jing Wang, Haobo Chen