Patents by Inventor Haoqi Ren
Haoqi Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9262164Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.Type: GrantFiled: May 1, 2015Date of Patent: February 16, 2016Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20150356025Abstract: A digital system including a processor core and a cache control unit is disclosed. The processor core is capable of being coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data. Further, the cache control unit is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: KENNETH CHENGHAO LIN, HAOQI REN
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Patent number: 9141388Abstract: A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information.Type: GrantFiled: July 13, 2012Date of Patent: September 22, 2015Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO., LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Patent number: 9141553Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions.Type: GrantFiled: July 29, 2014Date of Patent: September 22, 2015Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20150234660Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.Type: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Inventors: KENNETH CHENGHAO LIN, HAOQI REN
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Patent number: 9047193Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.Type: GrantFiled: January 28, 2011Date of Patent: June 2, 2015Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20140337582Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions.Type: ApplicationFiled: July 29, 2014Publication date: November 13, 2014Inventors: KENNETH CHENGHAO LIN, HAOQI REN
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Patent number: 8847615Abstract: A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.Type: GrantFiled: March 19, 2010Date of Patent: September 30, 2014Assignee: Shanghai Xinhao (Bravechips) Micro Electronics Co. Ltd.Inventors: Kenneth ChengHao Lin, Hongxi Geng, Haoqi Ren, Bingchun Zhang, Changchun Zhen
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Patent number: 8825958Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions.Type: GrantFiled: August 8, 2013Date of Patent: September 2, 2014Assignee: Shanghai Xin Hao Micro Electronics Co. Ltd.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20130339611Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions.Type: ApplicationFiled: August 8, 2013Publication date: December 19, 2013Applicant: Shanghai Xin Hao Micro Electronics Co., Ltd.Inventors: KENNETH CHENGHAO LIN, HAOQI REN
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Patent number: 8527707Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions.Type: GrantFiled: December 22, 2010Date of Patent: September 3, 2013Assignee: Shanghai Xin Hao Micro Electronics Co. Ltd.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20130185545Abstract: A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information.Type: ApplicationFiled: July 13, 2012Publication date: July 18, 2013Applicant: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: KENNETH CHENGHAO LIN, HAOQI REN
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Patent number: 8468335Abstract: A reconfigurable data processing platform is disclosed. The reconfigurable data processing platform includes a reconfigurable universal data processing module, a configuration memory, and a reconfiguration control unit. The reconfigurable universal data processing module contains a plurality of basic units each capable of being configured to perform a unit of at least one of a logic operation and an arithmetic operation. The configuration memory is coupled to the reconfigurable universal data processing module to provide configuration information to be used to configure the plurality of basic units. Further, the reconfiguration control unit is coupled to the reconfigurable universal data processing module and the configuration memory to provide control signals for configuration of the plurality of basic units.Type: GrantFiled: July 21, 2011Date of Patent: June 18, 2013Assignee: Shanghai Xin Hao Micro Electronics Co. Ltd.Inventors: Kenneth Chenghao Lin, Haoqi Ren, Zhongmin Zhao, Bingchun Zhang, Changchun Zheng
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Publication number: 20130111137Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.Type: ApplicationFiled: January 28, 2011Publication date: May 2, 2013Applicant: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20120278590Abstract: A reconfigurable processor is provided. The reconfigurable processor includes a plurality of functional blocks configured to perform corresponding operations. The reconfigurable processor also includes one or more data inputs coupled to the plurality of functional blocks to provide one or more operands to the plurality of functional blocks, and one or more data outputs to provide at least one result outputted from the plurality of functional blocks.Type: ApplicationFiled: January 7, 2011Publication date: November 1, 2012Applicant: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Zhongmin Zhang, Haoqi Ren
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Publication number: 20120191967Abstract: A reconfigurable data processing platform is disclosed. The reconfigurable data processing platform includes a reconfigurable universal data processing module, a configuration memory, and a reconfiguration control unit. The reconfigurable universal data processing module contains a plurality of basic units each capable of being configured to perform a unit of at least one of a logic operation and an arithmetic operation. The configuration memory is coupled to the reconfigurable universal data processing module to provide configuration information to be used to configure the plurality of basic units. Further, the reconfiguration control unit is coupled to the reconfigurable universal data processing module and the configuration memory to provide control signals for configuration of the plurality of basic units.Type: ApplicationFiled: July 21, 2011Publication date: July 26, 2012Applicant: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren, Zhongmin Zhao, Bingchun Zhang, Changchun Zheng
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Publication number: 20110238917Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory.Type: ApplicationFiled: December 22, 2010Publication date: September 29, 2011Applicant: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.Inventors: Kenneth Chenghao Lin, Haoqi Ren
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Publication number: 20100237891Abstract: A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.Type: ApplicationFiled: March 19, 2010Publication date: September 23, 2010Inventors: Kenneth ChengHao Lin, Hongxi Geng, Haoqi Ren, Bingchun Zhang, Changchun Zhen