Abstract: A parallel system for performing LMS coefficient adaptation includes a data memory, a tap memory, and two or more LMS hardware units. The LMS hardware units utilize data stored in the data memory and coefficients stored in the tap memory for performing multiple LMS coefficient adaptations in parallel.

Abstract: A protocol processor for processing first header information of a reception packet to provide instructions for processing second header data of a reception packet is provided. For efficient protocol processing, special hardware architectures are necessary. Hardware architectures for dynamic length input buffer, no penalty conditional jump, one clock-cycle case-based jump, accumulated partial comparison, and integrated layer processing on-the-fly are described. The architectures are used in a domain-specific protocol processor, which is based on program controlled execution. The processor does not operate on data stored in a memory, but on an incoming packet-flow with constant speed. The processor performs every instruction in one clock-cycle, including conditional jump (taken and not taken) and case based jump.

Abstract: A system and method for accelerating least-mean-square algorithm-based coefficient adaptation which executes in one machine clock cycle one tap of the least-mean-square algorithm including data fetch, coefficient fetch, coefficient adaptation, convolution, and write-back of a new coefficient vector. A data memory stores an input signal. A coefficient memory stores a coefficient vector. A multiplication and accumulation unit reads the input signal from the data memory and the coefficient vector from the coefficient memory to perform convolution.

Abstract: A protocol processor for processing first header information of a reception packet to provide instructions for processing second header data of a reception packet is provided. For efficient protocol processing, special hardware architectures are necessary. Hardware architectures for dynamic length input buffer, no penalty conditional jump, one clock-cycle case-based jump, accumulated partial comparison, and integrated layer processing on-the-fly are described. The architectures are used in a domain-specific protocol processor, which is based on program controlled execution. The processor does not operate on data stored in a memory, but on an incoming packet-flow with constant speed. The processor performs every instruction in one clock-cycle, including conditional jump (taken and not taken) and case based jump.