Abstract: The present invention relates to a polarization filter which is formed by at least one periodic line grid made from parallel extending metallic webs on a dielectric layer. The metallic webs are interrupted in their longitudinal extension by slots. The centre-to-centre distances between the slots are greater than the period of the line grid in a direction parallel to the metallic webs. The proposed polarization filter can be produced with a CMOS process with high reliability, in particular for the visible spectral range, even over a larger area.

Abstract: A capacitive voltage divider arrangement includes a first and second voltage divider and a first and second parasitic capacitance formed between the first and second capacitive voltage divider. The first capacitive voltage divider includes: a signal terminal; first capacitance for coupling the terminal to a reference potential; second capacitance; and third capacitance that is coupleable to the reference potential, the second capacitance being coupled in-between the terminal and third capacitance.

Abstract: A hybrid analog-to-digital converter includes a plurality of converting circuits. Each converting circuit is configured to provide a digital signal based on an analog input signal by performing a successive approximation conversion to obtain, as a result of the successive approximation conversion, a first number of bits of the digital signal, and by subsequently performing a slope conversion based on a common variable reference voltage to obtain a second number of bits of the digital signal, the second number of bits corresponding to a residual between the analog input signal and the result of the successive approximation conversion. The hybrid analog-to-digital converter further includes a common variable reference voltage provider configured to provide to each converting circuit of the plurality of converting circuits the common variable reference voltage.

Abstract: A capacitive voltage divider arrangement comprising a first and second voltage divider, a first and second parasitic capacitance being formed between the first and second capacitive voltage divider. The first capacitive voltage divider comprises a signal terminal; a first capacitance for coupling the terminal to a reference potential; a second capacitance; a third capacitance that may be coupled to the reference potential, the second capacitance being coupled in between the terminal and third capacitance.

Abstract: A hybrid analog-to-digital converter includes a plurality of converting circuits. Each converting circuit is configured to provide a digital signal based on an analog input signal by performing a successive approximation conversion to obtain, as a result of the successive approximation conversion, a first number of bits of the digital signal, and by subsequently performing a slope conversion based on a common variable reference voltage to obtain a second number of bits of the digital signal, the second number of bits corresponding to a residual between the analog input signal and the result of the successive approximation conversion. The hybrid analog-to-digital converter further includes a common variable reference voltage provider configured to provide to each converting circuit of the plurality of converting circuits the common variable reference voltage.

Abstract: A gateway (1000a) is provided including a telephony interface (1004), a network interface (1002), and a digital signal processor (DSP) (1008a) for encoding the incoming telephony channels. The telephony interface (1004) is configured to separate an incoming data stream into separate channels. The telephony interface (1004) is further configured to control operation of a plurality of clocks for synchronizing the transfer of the channels to the encoding DSP, thereby minimizing multiplexing delay. According to another embodiment, the incoming channels are separately initialized by a controller 1050, at a predetermined delay.