Patents by Inventor Harbans Sachdev

Harbans Sachdev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080026594
    Abstract: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing depositing a first layer of a first predetermined thickness of a spin-on dielectric on the metal layer protected with a plasma deposited silicon oxide SiOx. Next a thin stress relief layer of a second predetermined thickness is disposed on the first layer of spin-on-dielectric. Upon the thin stress-relief layer, a second layer of a third predetermined thickness of spin-on dielectric is deposited. Low-k spin-on dielectrics may include hydrogen silsequioxane (HSQ) and methyl silsequioxane (MSQ).
    Type: Application
    Filed: June 8, 2005
    Publication date: January 31, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Harbans Sachdev, Howard Shillingford, Garkay Leung, Mary Matera-Longo, John Rapp
  • Publication number: 20070161521
    Abstract: Liquid compositions containing a specific hindered phenol or a hindered phenol in combination with an aromatic phosphite are provided which are used as a thermal interface between a heatsink and a chip during a test procedure for electronic components which compositions enhance the thermal conductivity between the heatsink and the chip, are easily removed from the heatsink and the chip after the test procedure without any deleterious residue and which allow the use of high temperatures for extended periods during the test procedure without any significant degradation of the composition. A method for using the compositions in electronic component test procedures such as burn-in procedures is also provided.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 12, 2007
    Inventors: Krishna Sachdev, Mark Chace, Normand Cote, David Gardell, Jeffrey Gelorme, Sushumna Iruvanti, G. Lawson, Tuknekah Noble, Harbans Sachdev
  • Patent number: 5976710
    Abstract: A multilevel high density interconnect structure of a semiconductor device or package including a substrate having at least one conductive feature therein, a film of a polyimide composition on the substrate and selected from the group consisting of a cured product of a polyamic acid and a cured product of a polyamic ester. The polyamic acid is prepared by reacting a stoichiometric excess of a linear aromatic diamine and aromatic dianhydride to form a first reaction product where the molar ratio of said diamine to said aromatic anhydride is in the range from 100:97 to 100:99.5 and then reacting the first reaction product with an aromatic anhydride. The polyamic ester is prepared by reacting a stoichiometric excess of a linear aromatic diamine and an aromatic diester diacyl chloride to form a second reaction product where the molar ratio of said diamine to said diester diacyl chloride is in the range from 100:97 to 100:99.5 and then reacting the second reaction product with aromatic anhydride.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: November 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: Krishna Gandhi Sachdev, John Patrick Hummel, Sundar Mangalore Kamath, Robert Neal Lang, Anton Nendaic, Charles Hampton Perry, Harbans Sachdev