Abstract: A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net that includes a plurality of nodes to be interconnected. The interconnected nodes are designed to meet system requirements, commonly expressed by a set of wiring rules, include among others, physical, electrical and noise constraints. The method includes matching interconnection net attributes to wiring rule logical definitions, wherein the wiring rules include rule nodes and rule connections. The rule nodes define constraints for the pins, vias and cluster point structures. The rule connections define wiring constraints between the node structures to establish the net topology. The process described is based on net ordering and checking. The net ordering, which defines the pin-to-pin connections based on the wiring rule, is performed prior to chip or package wiring.