Abstract: The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program's behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.

Abstract: The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program's behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.

Abstract: The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program's behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.

Abstract: A method and apparatus for converting a source executable code generated for execution on a source processor into a target executable code for execution on a target processor is provided. Typically, the following sequence of steps are performed on a computer for each instruction in the source executable code. Initially, a source instruction is selected from the source executable code. This source instruction typically has an opcode and one or more corresponding parameters used by the opcode during execution. Next, the source instruction opcode is used to isolate one or more corresponding parameters within the source instruction. After this is completed, one or more target instructions associated with the target processor are located which correspond to the source instruction. Then, a target instruction is generated by filling the one or more parameters isolated from the source instruction into the corresponding parameter locations in the one or more target instructions.

Abstract: The present invention provides a method and apparatus for using input data to optimize a computer program. Initially, the computer program is divided into one or more logical units of code. Next, a CPU simulator is used to simulate execution of each logical unit using the input data. The output from the simulation is used to generate a first optimization metric value and corresponding state information for each logical unit. In one embodiment, the first optimization metric value and corresponding state information are stored in a first optimization vector. Using well known optimization techniques, the instructions within each logical unit are optimized iteratively until additional optimizations would result in very small incremental performance improvements. A second simulation is performed using the same input data except that this time the optimized logical units are used. This second simulation is used to measure how much the optimizer has improved the code.

Abstract: A method and apparatus for transforming a source executable code optimized for a source processor into a target executable code optimized for execution on a target processor is provided. Initially, the source executable is converted into a functionally equivalent source executable capable of execution on the target processor. Next, execution performance information for each basic block of code in the functionally equivalent source executable code is collected. Similarly, execution performance information for each basic block of code in an initial target executable code is also collected. As a next step, an optimization metric is generated for each basic block of code within the functionally equivalent source executable code and for each basic block of code within the initial target executable code. These optimization metrics are used to compare basic blocks in the functionally equivalent source executable code with basic block of code within the initial target executable code.