Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

Abstract: A half-duplex transceiver includes an antenna, antenna-side transformer windings coupled to the antenna, and a low-noise amplifier coupled to the antenna by the antenna-side transformer windings.

Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

Abstract: A half-duplex transceiver includes an antenna, antenna-side transformer windings coupled to the antenna, and a low-noise amplifier coupled to the antenna by the antenna-side transformer windings.

Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

Abstract: A half-duplex transceiver includes an antenna, antenna-side transformer windings coupled to the antenna, and a low-noise amplifier coupled to the antenna by the antenna-side transformer windings.

Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.

Abstract: Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.

Abstract: Two hysteresis levels, a high level and a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using pairs of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.

Abstract: As disclosed herein, two hysteresis levels, a high level a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using a set of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.

Abstract: An output stage of a switching DC-DC converter includes a pair of transistors and a bias transistor connected between the transistors. A voltage regulator generates a bias voltage to bias a control terminal of the bias transistor with a fixed bias voltage. The voltage regulator is operable in a full-power mode and a low-power mode. The voltage regulator consumes larger current in the full-power mode than in the low-power mode. At low load currents, the voltage regulator is operated in the low-power mode when both the transistors in the pair of transistors are off, and in the full-power mode otherwise.

Abstract: An output stage of a switching DC-DC converter includes a pair of transistors and a bias transistor connected between the transistors. A voltage regulator generates a bias voltage to bias a control terminal of the bias transistor with a fixed bias voltage. The voltage regulator is operable in a full-power mode and a low-power mode. The voltage regulator consumes larger current in the full-power mode than in the low-power mode. At low load currents, the voltage regulator is operated in the low-power mode when both the transistors in the pair of transistors are off, and in the full-power mode otherwise.

Abstract: A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the LDO regulators including a resistor scaling array for generating candidate voltages based on a first output voltage of the LDO regulators, a multiplexer for forwarding one of the candidate voltages selected by a binary search algorithm, and a comparator for generating a first test output by comparing the candidate voltage with an external reference voltage, and a DC load regulation measurement module for measuring corresponding DC regulation voltages of the LDO regulators including a switch for applying an internal test load to a second output voltage of the LDO regulators, and the comparator for generating a second test output by comparing a reference voltage with the second output voltage modified by the internal test load.

Abstract: A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the LDO regulators including a resistor scaling array for generating candidate voltages based on a first output voltage of the LDO regulators, a multiplexer for forwarding one of the candidate voltages selected by a binary search algorithm, and a comparator for generating a first test output by comparing the candidate voltage with an external reference voltage, and a DC load regulation measurement module for measuring corresponding DC regulation voltages of the LDO regulators including a switch for applying an internal test load to a second output voltage of the LDO regulators, and the comparator for generating a second test output by comparing a reference voltage with the second output voltage modified by the internal test load.