Abstract: Techniques are described for performing transformation on video data. A transform circuit may receive M sample values of the video data from a pre-transform buffer, and process the M sample values with N computation units of the transform circuit to generate intermediate values. Processing the M sample values to generate the intermediate values includes feeding back temporary values from output of one or more of the N computation units to input of one or more of the N computation units. The transform circuit may store a first set of the intermediate values in a transpose buffer, and store a second set of the intermediate values in the pre-transform buffer that are to be later retrieved for storage in the transpose buffer.

Abstract: Systems and methods implemented in firmware and hardware domains may include writing by the firmware domain configuration information to a memory for a plurality of passes of hardware processing, programming by the hardware domain configuration registers with the configuration information retrieved from the memory, and processing by the hardware domain the plurality of passes in accordance with the configuration information programmed in the configuration registers. The configuration registers may be programmed after the configuration information are written to the memory.

Abstract: Methods, systems, and devices for motion analysis are described. Generally, the described techniques provide for computationally efficient and accurate motion analysis. A device may identify frames of a video frame sequence having a defined resolution. The device may downscale the frames to generate a plurality of downsampled images each having a resolution lower than the defined resolution. The device may generate a respective histogram vector for each pixel of each downsampled image and each pixel of the original frames. The device may determine a motion vector candidate based at least in part on the histogram vectors. The device may apply a filter to the motion vector candidates to determine a final motion vector and output an indication of motion between the frames of the video frame sequence based at least in part on the final motion vector for each pixel of the second frame.

Abstract: Example video encoding techniques are described. A video encoder may generate residual data for macroblocks for tiles of a current frame. Each tile includes a plurality of macroblocks, each tile is independently encoded from the other tiles of the current frame, and a width of each tile is less than a width of the current frame. The video encoder may store the residual data in buffers. Each buffer is associated with one or more tiles, and each buffer is configured to store residual data for macroblocks for the one or more tiles with which each buffer is associated. The video encoder may read the residual data from the plurality of buffers for macroblocks of an entire row of the current frame before reading residual data from the plurality of buffers for macroblocks of any other row of the current frame, and encode values based on the read residual data.

Abstract: A technique for decoding data within a context-based adaptive binary arithmetic coding (CABAC) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable CABAC decoder circuit cascades one or more instances of CABAC bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency. The decoder may advantageously select among different combinations of decoder clock frequency and decoded bins per clock cycle to minimize power consumption associated with decompressing and playing the compressed data.

Abstract: Techniques are described for performing transformation on video data. A transform circuit may receive M sample values of the video data from a pre-transform buffer, and process the M sample values with N computation units of the transform circuit to generate intermediate values. Processing the M sample values to generate the intermediate values includes feeding back temporary values from output of one or more of the N computation units to input of one or more of the N computation units. The transform circuit may store a first set of the intermediate values in a transpose buffer, and store a second set of the intermediate values in the pre-transform buffer that are to be later retrieved for storage in the transpose buffer.

Abstract: Various embodiments of methods and systems for out-of-stream-order compression of multi-media data tiles in a system on a chip (“SoC”) of a portable computing device (“PCD”) are disclosed. In an exemplary method an input data transaction comprising an uncompressed data tile is received. A header pixel of at least one sub-tile of the received uncompressed data tile is extracted, where the sub-tile comprises a plurality of data blocks received in an input order. The plurality of data blocks are encoded in the input order, an Idx code for each of the plurality of encoded data blocks is stored in a stream buffer. The header pixel, a BFLC code for each of the plurality of encoded data blocks, and the Idx code for each of the plurality of encoded data blocks from the stream buffer are packed into an output format.

Abstract: A technique for decoding data within a context-based adaptive binary arithmetic coding (CABAC) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable CABAC decoder circuit cascades one or more instances of CABAC bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency. The decoder may advantageously select among different combinations of decoder clock frequency and decoded bins per clock cycle to minimize power consumption associated with decompressing and playing the compressed data.

Abstract: A hardware multi-stream multi-standard video decoder device. A command parser accesses a plurality of video streams, identifies a video encoding standard used for encoding video streams of the plurality of video streams, and interleaves portions of the plurality of video streams. A plurality of hardware decoding blocks perform operations associated with decoding the plurality of video streams, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards, such that interleaved video streams are decoded by activating subsets of the plurality of hardware decoding blocks for use in decoding the plurality of video streams. A plurality of register sets store parameters associated with the plurality of video streams.

Abstract: A hardware multi-standard video decoder device. A command parser accesses a video stream and identifies a video encoding standard used for encoding the video stream. A plurality of hardware decoding blocks perform operations associated with decoding the video stream, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards.

Abstract: A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.