Patents by Inventor Harish Dangat

Harish Dangat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LEAKAGE POWER REDUCTION IN INTEGRATED CIRCUITS BY SELECTIVE REMOVAL AND/OR SIZING OF SWITCH CELLS
    Publication number: 20150213179
    Abstract: According to one general aspect, a method may include receiving a placed and routed circuit design, wherein the placed and routed circuit design includes a plurality of switch cells. The method may include performing a supply voltage drop analysis on the placed and routed circuit design. The method may also include creating a voltage drop map detailing a plurality of supply voltage drops across the placed and routed circuit design as a function of physical position. The method may further include determining one or more low voltage drop portions of the placed and routed circuit design that are associated with respective voltage drops below a predetermined threshold value. The method may include altering one or more switch cells included by the respective one or more low voltage portions.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 30, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Harish DANGAT, Prasanth KODURI, Sarita BASWANT
  • INTEGRATED CIRCUIT LAYOUTS AND METHODS TO REDUCE LEAKAGE
    Publication number: 20150186585
    Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.
    Type: Application
    Filed: March 27, 2014
    Publication date: July 2, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Harish DANGAT, Young KOOG, Sarita BASWANT, Prasanth KODURI
  • Integrated circuit layouts and methods to reduce leakage
    Patent number: 9058459
    Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Harish Dangat, Young Koog, Sarita Baswant, Prasanth Koduri
  • Architecture and logic to control a device without a JTAG port through a device with a JTAG port
    Patent number: 6757844
    Abstract: An apparatus comprising a first circuit comprising a JTAG port and a second port. A JTAG non-compliant circuit may be controlled by the JTAG port when connected to the second port.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Navaz Lulla, Anup Nayak, Harish Dangat, Richard L. Stanton
  • PLD configuration port architecture and logic
    Patent number: 6748456
    Abstract: A programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the PLD in response to the data.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 8, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Richard L. Stanton, Anup Nayak, Navaz Lulla, Harish Dangat
  • Parallel configuration method and/or architecture for PLDs or FPGAs
    Patent number: 6507213
    Abstract: A programmable logic device comprising a plurality of configuration blocks that may be configured to store configuration information for configuring the programmable logic device. The configuration blocks may be simultaneously programmed.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: January 14, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventor: Harish Dangat