Abstract: Systems, devices and methods are disclosed for an ultra-wide-band (UWB) transmitter tag capable of operating in different power mode depending on voltage level and/or host interruption signal. The transmitter tag comprises a power management circuit, a one-time-programmable memory (OTP), a read/write memory, a state machine for controlling/monitoring the operation of the tag. The tag goes into the high power mode when the power supply ramps up to a preset voltage level. During the high power mode, the tag consumes the higher level of electrical current as indicated by the battery current signal. Upon completion of high power consumption activity, such as OTP memory download, the tag exits the high power mode and enters the low power mode. The power supply current goes to the low level to minimize the power consumption by the tag.

Abstract: Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power-good-detector, a first regulator and a second regulator. The power-good-detector includes a power-good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.

Abstract: Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power-good-detector, a first regulator and a second regulator. The power-good-detector includes a power-good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.

Abstract: Systems, devices and methods are disclosed for an ultra-wide-band (UWB) transmitter tag capable of operating in different power mode depending on voltage level and/or host interruption signal. The transmitter tag comprises a power management circuit, a one-time-programmable memory (OTP), a read/write memory, a state machine for controlling/monitoring the operation of the tag. The tag goes into the high power mode when the power supply ramps up to a preset voltage level. During the high power mode, the tag consumes the higher level of electrical current as indicated by the battery current signal. Upon completion of high power consumption activity, such as OTP memory download, the tag exits the high power mode and enters the low power mode. The power supply current goes to the low level to minimize the power consumption by the tag.

Abstract: Techniques for detecting jammer signals in a received signal are described. In one aspect, high-speed current mirror resistive compensation circuits and output impedance boosting circuits are utilized to increase amplifier bandwidth in an improved wideband amplifier circuit. In another aspect, a dual transistor configuration including common source topology, averaging capacitors and a comparator circuit is utilized to improve the sensing of signal peaks in a peak detector block, which can be used together with the wideband amplifier circuit and a digital jammer detection circuit to detect jammer signals. The digital jammer detection circuit aids in the determination of the presence of jammer signals within the received signal, the determination of which may be variable due to programmability of the digital jammer detection circuit as described.

Abstract: An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.

Abstract: The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.

Abstract: An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

Abstract: A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.

Abstract: A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Abstract: A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.

Abstract: Techniques for designing a low-noise amplifier (LNA) for operation over a wide range of input power levels. In an exemplary embodiment, a first gain path is provided in parallel with a second gain path. The first gain path includes a differential cascode amplifier with inductor source degeneration. The second gain path includes a differential cascode amplifier without inductor source degeneration. The cascode transistors of the gain paths may be selectively biased to enable or disable the first and/or second gain path. By selectively biasing the cascode transistors and input transistors, various combinations of the first and second gain paths may be selected to provide an optimized gain configuration for any input power level.

Abstract: A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Abstract: Techniques for detecting jammer signals in a received signal are described. In one aspect, high-speed current mirror resistive compensation circuits and output impedance boosting circuits are utilized to increase amplifier bandwidth in an improved wideband amplifier circuit. In another aspect, a dual transistor configuration including common source topology, averaging capacitors and a comparator circuit is utilized to improve the sensing of signal peaks in a peak detector block, which can be used together with the wideband amplifier circuit and a digital jammer detection circuit to detect jammer signals. The digital jammer detection circuit aids in the determination of the presence of jammer signals within the received signal, the determination of which may be variable due to programmability of the digital jammer detection circuit as described.

Abstract: Techniques for designing a low-noise amplifier (LNA) for operation over a wide range of input power levels. In an exemplary embodiment, a first gain path is provided in parallel with a second gain path. The first gain path includes a differential cascode amplifier with inductor source degeneration. The second gain path includes a differential cascode amplifier without inductor source degeneration. The cascode transistors of the gain paths may be selectively biased to enable or disable the first and/or second gain path. By selectively biasing the cascode transistors and input transistors, various combinations of the first and second gain paths may be selected to provide an optimized gain configuration for any input power level.