Patents by Inventor Harminder Banwait

Harminder Banwait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8098735
    Abstract: A circuit generally having a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 8×8 CABAC residual block. The second module may be configured to generate a scanning position signal based on the metric signals. The third module may be configured to generating a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks in an output signal by sub-sampling the parsed residual blocks based on the scanning position signal.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 17, 2012
    Assignee: LSI Corporation
    Inventors: Jamal Benzreba, Harminder Banwait, Eric Pearson
  • Publication number: 20080152015
    Abstract: A circuit generally having a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 8×8 CABAC residual block. The second module may be configured to generate a scanning position signal based on the metric signals. The third module may be configured to generating a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks in an output signal by sub-sampling the parsed residual blocks based on the scanning position signal.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Inventors: Jamal Benzreba, Harminder Banwait, Eric Pearson
  • Publication number: 20080112488
    Abstract: An apparatus generally having a reference memory and a motion estimation circuit is disclosed. The reference memory may store reference samples used in a motion estimation of a current block beyond a boundary of a picture. The motion estimation circuit may (i) buffer the reference samples as copied from the reference memory, the reference samples as buffered residing both (a) inside the boundary and (b) inside a search window of the motion estimation, (ii) shift a sub-set of the reference samples to align with a corner of a sub-window, the sub-window being (a) completely within the search window and (b) at least partially outside of the boundary, (iii) fill an empty portion of the sub-window with copies of the reference samples within the sub-set and (iv) generate difference values by comparing the current block against the reference samples within the sub-window a plurality of times.
    Type: Application
    Filed: January 15, 2008
    Publication date: May 15, 2008
    Inventors: Eric Pearson, Harminder Banwait, Michael Gallant
  • Patent number: 7369066
    Abstract: A circuit generally including a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 4×4 CAVLC residual blocks. The second module configured to generate a plurality of scanning position signals based on the metric signals. The third module configured to generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling the parsed residual blocks based on the scanning position signals.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Jamal Benzreba, Harminder Banwait, Eric Pearson
  • Publication number: 20070183491
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.
    Type: Application
    Filed: January 12, 2006
    Publication date: August 9, 2007
    Inventors: Eric Pearson, Harminder Banwait
  • Patent number: 7026961
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more of a context index and a binary symbol. The second circuit may be configured to generate a series of output bits in response to the plurality of signals. The memory may be configured to transfer the plurality of signals between the first circuit and the second circuit.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Eric Pearson, Michael D. Gallant, Harminder Banwait
  • Publication number: 20050258982
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more of a context index and a binary symbol. The second circuit may be configured to generate a series of output bits in response to the plurality of signals. The memory may be configured to transfer the plurality of signals between the first circuit and the second circuit.
    Type: Application
    Filed: May 3, 2004
    Publication date: November 24, 2005
    Inventors: Eric Pearson, Michael Gallant, Harminder Banwait
  • Publication number: 20050232505
    Abstract: A method for controlling an arithmetic codec context is disclosed. The method may include the steps of (A) reading a current value indicating one of a first condition and a second condition corresponding to a current context of a plurality of predetermined contexts, (B) generating an input state matching (i) an initial state in response to the first condition and (ii) an output state in response to the second condition, wherein the initial state has a predetermined value and the output state has a value generated by the method before receiving the current context and (C) generating a current output state by performing an arithmetic code operation on an input signal using the input state.
    Type: Application
    Filed: April 14, 2004
    Publication date: October 20, 2005
    Inventors: Eric Pearson, Harminder Banwait
  • Publication number: 20050013362
    Abstract: An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a boundary of a picture stored in a second memory, (ii) copy a first plurality of reference samples in the search window from the second memory to the first memory and (iii) map a plurality of reads from the first memory for a plurality of pad samples to the reference samples in the first memory, where the pad samples are determined to be outside the boundary.
    Type: Application
    Filed: October 9, 2003
    Publication date: January 20, 2005
    Inventors: Eric Pearson, Harminder Banwait, Michael Gallant