Patents by Inventor Harold Garth Nash

Harold Garth Nash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4070631
    Abstract: A digital noise blanking circuit for use in generating a single output pulse in response to a noisy signal which may include clusters of noise-induced pulses, the circuit utilizing a digital counter which is operated for a preset period of time longer than the time during which noise-induced transitional pulses may occur.
    Type: Grant
    Filed: November 26, 1976
    Date of Patent: January 24, 1978
    Assignee: Motorola Inc.
    Inventors: Harold Garth Nash, Jack Whitmore
  • Patent number: 4061885
    Abstract: A digital tone decoder includes means for generating a timing signal, zero crossing counter means for generating a decode signal after a predetermined number of zero crossings in response to an incoming time domain signal and for generating a reset signal at a predetermined time after the decode signal is sent to reset said zero crossing counter means to zero, and decoder means coupled to said zero crossing counter and to said timing means for generating an output signal at one of a plurality of output terminals corresponding to the frequency of the incoming signal upon receipt of the decode signal from said zero crossing counter means, said decoder means being reset to an initial state upon receipt of the reset signal.
    Type: Grant
    Filed: December 17, 1975
    Date of Patent: December 6, 1977
    Assignee: Motorola, Inc.
    Inventors: Harold Garth Nash, Jack Whitmore
  • Patent number: 4008373
    Abstract: A digital control circuit means responsive to a timing signal and a phase shift control signal accepts digital dibits of data and generates a digital control output signal. A digital phase shifter coupled to the control circuit and responsive to a timing signal generates a main and a secondary channel digital output signal alternately at a first and a second output terminal during successive dibit intervals. The main channel digital output signal is phase shifted a predetermined amount with respect to a main channel digital output signal generated during a preceding dibit interval in response to said digital control output signal. A multiplexer coupled to the first and second output terminals of the phase shifter transmits the main channel digital output signal on a third output terminal and the secondary channel digital output signal on a fourth output terminal.
    Type: Grant
    Filed: October 3, 1975
    Date of Patent: February 15, 1977
    Assignee: Motorola, Inc.
    Inventors: Harold Garth Nash, Gene Arnold Schriber, John Robert Linford
  • Patent number: 3997855
    Abstract: A digital FSK time rate change modulator is responsive to a digital input signal and generates either a first or a second output frequency. The FSK modulator switches from one output frequency to the other in small increments over a predetermined time interval. The FSK modulator includes means for generating a first and a second timing signal and input means for receiving the digital input signal. An up-down counter having an up-count input and a down-count input counts up and down between a first and a second state. First gating means is coupled to the output of the up-down counter and to the input means and passes the second timing signal to the up-count input when a high level digital input signal is present on the input means and the up-down counter is not in the second state.
    Type: Grant
    Filed: December 24, 1975
    Date of Patent: December 14, 1976
    Assignee: Motorola, Inc.
    Inventor: Harold Garth Nash