Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Abstract: One-time programmable (OTP) Electronically Programmable Read-Only Memories (EPROMs) have been used in a number of applications for many years. One drawback with these OTP EPROMs is that these nonvolatile memories tend to be slow and/or may use a considerable amount of area. Here, however, a bit cell is provided that employs a compact dual cell, which generally includes two OTP cells. These OTP cells are generally arranged in differential configuration to increase speed and are arranged to have a small impact on area.

Abstract: One-time programmable (OTP) Electronically Programmable Read-Only Memories (EPROMs) have been used in a number of applications for many years. One drawback with these OTP EPROMs is that these nonvolatile memories tend to be slow and/or may use a considerable amount of area. Here, however, a bit cell is provided that employs a compact dual cell, which generally includes two OTP cells. These OTP cells are generally arranged in differential configuration to increase speed and are arranged to have a small impact on area.

Abstract: An improved grape storage and handling bag is disclosed. The bag has increased size and reduced venting. The bag of the invention has holes on one or both side walls of the bag to provide a percentage perforation ranging from 0.4 to 1.4%. The bag reduces water loss while still permitting SO.sub.2 ventilation. Grapes stored in the bags of this invention show reduced levels of water loss, stem browning, berry shatter, and decay. The grapes may be stacked in one or two layers. The bagged grapes are contained within a container and stacked in one or two layers within the containers.

Abstract: A circuit for presetting the voltage of an output terminal connected to an external load, where the output terminal receives either a high or a low voltage level state for output to the load during a data cycle, includes a voltage detector connected to the output terminal for sensing the voltage level at the output terminal at the end of the data cycle to determine whether the voltage level is at a high or a low voltage level state. A driver is connected to the voltage sensor for driving the voltage level at the output terminal prior to the start of a subsequent data cycle toward the opposite voltage state to a mid-level, as determined by the prior voltage state sensed by the voltage detector.

Abstract: A planar array of memory cells is controlled by row lines (word lines) for each row of cells and column lines each serving adjacent columns of cells as well as bit lines interlaced with the column lines so that all memory cells are connected between a column line and a bit line. The least significant bit of the column address provided by the column decoder selects between two sets of bit lines that are interlaced in altercation determining on which side of the column line the selected column will be found. In consequence, the selection of the column line and a set of bit lines selects only one column of cells. Enough columns of the array are selected at one time to address an entire logical field of data bits and also a set of parity bits related to the logical field of data bits.

Abstract: An integrated circuit having an option between two or more configurations and also using a patterned ion-implant for impressing data (such as a ROM section of the circuit) may advantageously perform the option-specification simultaneously with the ROM; using a powerless option-specifying circuit permits testing portions of the circuit before the implantation step.

Abstract: A buffer circuit accepting TTL input levels and generating logic-level signals incorporates means to reduce the power consumption in the circuit in the active phase as well as the inactive phase, without imposing additional restrictions on the user.

Abstract: In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17") from the sense amplifier (66) driven, in order to reduce its capacitive load, prior to the time of latching the information into the sense amplifier (66).

Abstract: A high speed parity circuit uses a sequence of simplified exclusive-OR circuits responsive to data input terminals containing a data signal and its complement and terminating in a sense amplifier, together with an operating sequence in which the inputs to the sequence are grounded while the data lines are first brought high and then set to the correct data state to form a pair of separate paths through the sequence when no current flows, after which set-up operation an input voltage circuit raises the voltage on one of the paths smoothly, so that the sense amplifier can respond as soon as its input is large enough, without waiting for a settling time.

Abstract: A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capacative load on the column decoder and saving space.

Abstract: An on-hook/off-hook detector circuit (10) is included within a telecommunications integrated circuit. A tone generator power signal (V.sub.G) is monitored as a status signal to determine when a telephone switch hook is in either an on-hook or off-hook condition. The tone generator power signal is subject to interference and transients which prevents direct utilization of it to indicate on-hook and off-hook conditions. A resistor (20) and capacitor (22) are connected externally to the circuit (10) at a junction terminal (16) to provide a time delay following a transition of the status signal (V.sub.G). The junction terminal of the resistor (20) and capacitor (22) is held at two transistor threshold voltages below the upper supply voltage (V+). At the time of transition of the status signal V.sub.G the junction terminal (16) is disconnected from a current path such that the terminal (16) is permitted to charge the capacitor (22) through the resistor (20).