Abstract: This invention allows a video network camera to be mounted directly against a window or other transparent surface without any additional mounting hardware. The network camera can be mounted both inside and outside of a window without additional mounting hardware. A novel mounting apparatus in conjunction with an adjustable video sensor allows the user to quickly mount and make adjustments to the viewing angle of the network camera, thus reducing installation time and installation costs. In addition, the network camera can be mounted to walls, ceilings and other surfaces as necessary by using a second mounting assembly.

Abstract: A novel MODEM and method of operating a MODEM usable in spread spectrum communication utilizing multiple waveforms in orthogonal spread signals imbeds a tracking signal in one of the spread signals for efficient tracking by a receiver so that both spread signals can have wideband characteristics. Therefore, one spread signal contains a tracking channel and a wideband channel, allowing for higher order modulation in the wideband channel for transmitting information, while still providing good tracking features. The second spread signal is an orthogonal wideband channel serving as the main high data rate conduit. In the preferred embodiment, the first portion of the waveform (in the first spread signal) is modulated using Bi-Bi-Phase Shift Keying (Bi-BPSK), while the second portion of the waveform (in the second spread signal) is modulated using Multiple Phase Shift Keying (MPSK). The two waveform portions are Time Division Multiplexed (TDM) at the chipping rate.

Abstract: A communications system comprising a central node, at least one remote node and a communications link. The remote node is adapted to receive information transmitted from the central node over a broadcast link and the communications link is adapted to convey information from the remote node to the central node. The central node is adapted to dynamically tailor a remote node transmit power control and a bandwidth as requested by the remote node for conveying information over the communications link.

Abstract: A novel MODEM and method of operating a MODEM usable in spread spectrum communication utilizing multiple waveforms in orthogonal spread signals imbeds a tracking signal in one of the spread signals for efficient tracking by a receiver so that both spread signals can have wideband characteristics. Therefore, one spread signal contains a tracking channel and a wideband channel, allowing for higher order modulation in the wideband channel for transmitting information, while still providing good tracking features. The second spread signal is an orthogonal wideband channel serving as the main high data rate conduit. In the preferred embodiment, the first portion of the waveform (in the first spread signal) is modulated using Bi-Bi-Phase Shift Keying (Bi-BPSK), while the second portion of the waveform (in the second spread signal) is modulated using Multiple Phase Shift Keying (MPSK). The two waveform portions are Time Division Multiplexed (TDM) at the chipping rate.

Abstract: A communications system comprising a central node, at least one remote node and a communications link. The remote node is adapted to receive information transmitted from the central node over a broadcast link and the communications link is adapted to convey information from the remote node to the central node. The central node is adapted to dynamically tailor a remote node transmit power control and a bandwidth as requested by the remote node for conveying information over the communications link.

Abstract: A novel programmable digital gain controller is provided for the automatic gain control loop of a communications receiver. The digital gain controller comprises a pair of digital detectors coupled to the real and imaginary components of a data stream for providing digital data magnitude output signals which are coupled to an adder whose output is coupled to a first input of a comparator having a second input coupled to a predetermined reference level command. The output of the comparator generates a digital error signal which is coupled to the input of a programmable gain accumulator having a second input proportional gain command so as to provide at the output of the programmable gain accumulator a digital gain command which may be coupled to a variable gain controlled amplifier which is connected in the input data stream of the channel of a communications receiver to provide a predetermine amplifier output level.

Abstract: A time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation an error signal indicative of a time magnitude difference between the analog transition time of the data and the chip strobe time multiplied by the sign of the data. The output of the early sample-late sample circuit is applied to a second accumulate and scale circuit for generating an accumulated error signal which is applied to an inverter. The inverter is provided with a decision directed tracking input indicative of the sign of the data sample and is employed to invert the accumulated error signal when the sign of the analog data is negative.

Abstract: A novel programmable digital acquisition and tracking controller is coupled to the input signal level from the demodulator of a communications receiver and provides programmable signal level threshold detectors and detection intervals adapted to produce an output signal which is indicative of the correlation between the received PN code and the locally generated PN code as compared against a programmable threshold. The programmable detector logic is capable of detecting acquisition correlation and tracking correlation and can optionally inform an external microprocessor of the correlation level so as to implement a wide variety of acquisition, tracking and reacquisition algorithms as well as optional AM demodulation.

Abstract: A novel accumulate and scale circuit is provided with an input accumulator which is only as wide as the input data stream. Additional most significant bits are generated to extend the output of the accumulate and scale circuit by providing and an up and down counter having a number of most significant bit stages. The adder stages of the input accumulator have their carry and borrow outputs coupled to the up and down counter for generating additional most significant bits.

Abstract: A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.

Abstract: A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.

Abstract: A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.

Abstract: A present invention novel frequency-phase discriminator has input channels for real and imaginary data which are coupled to two programmable despreaders. The first despreader has its real and imaginary outputs coupled to individual programmable data rate filters which have their individual outputs coupled to a quadrant detector that generates a phase angle direction signal and sign magnitude. The second despread has its real and imaginary outputs connected through individual programmable inverters to data rate filters which have their individual outputs coupled to a quadrant selector that selects error signal data rate information from one of four quadrant axes signals. A command generator is programmably coupled to the output of the quadrant detector and to the input of the quadrant selector and provides a selection signal to the quadrant selector which produces a frequency error signal output employed in a frequency lock loop or in a phase lock loop.