Abstract: In an embodiment, a power-supply controller includes a control circuit, a drive circuit, and a signal-drop-reducing circuit. The control circuit is configured to generate a drive signal having a duty cycle, and the drive circuit is configured to cause a phase circuit of a power supply to generate, in response to the drive signal, an output signal having a magnitude. And the signal-drop-reducing circuit is configured to disable the driver circuit in response to the duty cycle corresponding to a signal magnitude that is lower than the magnitude of the output signal. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, such a power-supply controller can reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.

Abstract: In an embodiment, a method includes generating a pulse-width-modulated signal having a duty cycle, and isolating a power-supply output node in response to the duty cycle corresponding to a signal magnitude that is less than a magnitude of an output signal on the power-supply output node. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, a power-supply controller can use such a technique to reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.

Abstract: In an embodiment, a power-supply controller includes a control circuit, a drive circuit, and a signal-drop-reducing circuit. The control circuit is configured to generate a drive signal having a duty cycle, and the drive circuit is configured to cause a phase circuit of a power supply to generate, in response to the drive signal, an output signal having a magnitude. And the signal-drop-reducing circuit is configured to disable the driver circuit in response to the duty cycle corresponding to a signal magnitude that is lower than the magnitude of the output signal. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, such a power-supply controller can reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.

Abstract: In an embodiment, a method includes generating a pulse-width-modulated signal having a duty cycle, and isolating a power-supply output node in response to the duty cycle corresponding to a signal magnitude that is less than a magnitude of an output signal on the power-supply output node. For example, where a power supply has a non-zero residual output signal (e.g., output voltage) on its output node after the power supply is deactivated, a power-supply controller can use such a technique to reduce or eliminate a drop in the residual output signal caused by, or that would be caused by, a restarting of the power supply.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.

Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.

Abstract: A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed.

Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.