Abstract: An integrated circuit 14 having an active circuit 19 is formed on a circuit wafer 10. A moat 18 in the field oxide 20 surrounds the active circuit 19. Metallic conductor 30 passes from a location on the active circuit 19 over the moat 18 to a contact area 22. The wafer 10 is covered with a photoshaped silicon nitride layer 18, and a support wafer 40 is secured with adhesive 46 to the circuit side of the circuit wafer 10. The circuit wafer 10 is photoshaped to expose the metallic conductor 30 at the contact area 22, and the contact area 22 is prepared with multiple metal layers 62, 66, 70 for connection to external wiring.

Abstract: A method for manufacturing an integrated circuit thermal print head is illustrated including transistor 20 and a resistor doped region 22 formed on a first surface of a silicon circuit wafer 10. A contamination barrier in the form of a moat 26 filled with silicon nitride 30 is formed around the transistor 20. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned, and the exposed surface of the circuit wafer 10 is photoshaped to define wafer segments 68 positioned over the resistor doped region 22.

Abstract: A read-only memory is manufactured from a matrix or array of multilayer electrical devices, each of which includes at least one metallic layer, a portion of which contacts a doped semi conductor region. The metallic layers are controllably and rapidly thinned down and decreased in cross-sectional area in the vicinity of the doped regions to form fusible links, thus producing a ROM starting product. Fusible link formation is enhanced by the use of an etchant for the metallic layer which forms an electrochemical cell in conjunction therewith and with the semiconductor and the doped region. Any metallic layers not contacting a doped region are also etched by the etchant, but at the much slower "chemical rate". Following the production of the starting product, a ROM may be produced by the selective application of voltages to selected fusible links, the I.sup.2 R heating of the links fusing them, or blowing them out. In a preferred embodiment, the electrical devices are MOSFETS.