Abstract: An analog input to an interpolation scheme for a digital signal processing receiver is digitized by an oversampling sigma-delta modulator running at a clock frequency that is a multiple of the nominal baud rate. The digitized signal sample stream and a delayed version thereof are shifted through finite impulse response (FIR) filters. The outputs of the FIR filters are coupled to a linear interpolator at a time determined by a carry-out of a divide-by-M counter, so as to decimate the digitized inputs to the FIR filters by the ratio of the oversampling clock to the baud clock. The control path to the interpolator includes a digital phase locked loop containing a linear canceler, to which data from an echo canceler and data decisions from an equalizer are supplied, and from which a timing error input is supplied to a loop filter.

Abstract: An analog input to an interpolation scheme for a digital signal processing receiver is digitized by an oversampling sigma-delta modulator running at a clock frequency that is a multiple of the nominal baud rate. The digitized signal sample stream and a delayed version thereof are shifted through finite impulse response (FIR) filters. The outputs of the FIR filters are coupled to a linear interpolator at a time determined by a carry-out of a divide-by-M counter, so as to decimate the digitized inputs to the FIR filters by the ratio of the oversampling clock to the baud clock. The control path to the interpolator includes a digital phase locked loop containing a linear canceler, to which data from an echo canceler and data decisions from an equalizer are supplied, and from which a timing error input is supplied to a loop filter.

Abstract: An analog input to an interpolation scheme for a digital signal processing receiver is digitized by an oversampling sigma-delta modulator running at a clock frequency that is a multiple of the nominal baud rate. The digitized signal sample stream and a delayed version thereof are shifted through finite impulse response (FIR) filters. The outputs of the FIR filters are coupled to a linear interpolator at a time determined by a carry-out of a divide-by-M counter, so as to decimate the digitized inputs to the FIR filters by the ratio of the oversampling clock to the baud clock. The control path to the interpolator includes a digital phase locked loop containing a linear canceler, to which data from an echo canceler and data decisions from an equalizer are supplied, and from which a timing error input is supplied to a loop filter.

Abstract: The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.

Abstract: The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.

Abstract: In a digital data receiver, it is desirable to use the equalized data for deriving time synchronization information. This invention minimizes timing contention between an equalizer operating at a T/2 rate and a timing recovery circuit which utilizes the output of the equalizer. An interpolator interpolates T1 and T2 data samples from the equalizer and provides data signals R and S equally spaced relative to the peak baud amplitude which can be easily processed by the timing recovery circuit.

Abstract: A modem receiver having receiver control, signal detection, and data demodulation implemented with a single general-purpose integrated circuit microcomputer. Novel multirate digital signal processing techniques are included which provide complete real-time recovery of all data and modem signals in a microcomputer integrated circuit having an architecture not optimized for signal processing applications. The resulting techniques extend to more general signal processing applications which may be implemented by other general-purpose microcomputers, programmed signal processors, or specific dedicated hardware logic. The novel modem receiver includes digital FIR filters, performing quadrature signal detection, and post-demodulation data correction with an all-digital second-order carrier recovery loop.