Patents by Inventor Harsh Singh
Harsh Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977918Abstract: The invention presents methods, systems and computer program products for optimizing computer system resource utilization during in-game resource farming. The invention comprises (i) detecting a gameplay event that triggers switching from a resource farming mode to a non-resource farming mode, or for switching from a non-resource farming mode to a resource farming mode, in connection with a runtime instance of a gaining application software, (ii) identifying a guest operating system within which the runtime instance of the gaming application software is being executed, (iii) selecting a mode switching protocol implementable within the identified guest operating system, and (iv) switching the runtime instance of the gaming application software from a resource farming mode to a non-resource farming mode, or from a non-resource farming mode to a resource farming mode, by implementing the selected mode switching protocol.Type: GrantFiled: August 26, 2021Date of Patent: May 7, 2024Assignee: NOW.GG, Inc.Inventors: Suman Saraf, Ravi Prakash, Harsh Singh
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Publication number: 20240143239Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.Type: ApplicationFiled: October 12, 2023Publication date: May 2, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Manuj AYODHYAWASI, Nitin CHAWLA
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Publication number: 20240136989Abstract: A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Harsh Sheokand, Tarunvir Singh, Anant Kamath, Suvadip Banerjee
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Publication number: 20240119053Abstract: In some examples, a system identifies sub-portions of a database query, assigns identifiers to the identified sub-portions, and adds the identifiers to a data structure. The system generates a fingerprint representing the database query based on applying a fingerprint function on the data structure including the identifiers.Type: ApplicationFiled: December 15, 2023Publication date: April 11, 2024Inventors: Shine Mathew, Ashish Dange, Harsh Singh, Lakshmi Pathy S. N.
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Publication number: 20240112748Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.Type: ApplicationFiled: July 31, 2023Publication date: April 4, 2024Applicant: STMicroelectronics International N.V.Inventors: Tanuj KUMAR, Hitesh CHAWLA, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240071546Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Hitesh CHAWLA, Tanuj KUMAR, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240069096Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.Type: ApplicationFiled: July 31, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Patent number: 11874834Abstract: A process includes accessing a query that is associated with joining a fact table with a plurality of dimension tables. The fact table includes a primary key that includes a set of columns, which are covered by the dimension tables. The process includes determining a query plan for processing the query. The query plan has an associated join order. Determining the query plan includes determining a plurality of sets of the plurality of dimension tables, where each set includes dimension tables, which cover the set of columns of the primary key. Determining the query plan includes evaluating costs that are associated with joining subsets of the plurality of sets with the fact table. Based on the costs, a given subset of the plurality of subsets is selected. Determining the query plan includes constraining the join order based on the given subset so that the dimension tables of the given subset are joined before the fact table.Type: GrantFiled: January 31, 2022Date of Patent: January 16, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Shine Mathew, Ashish Dange, Harsh Singh, Javeed Pasha
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Publication number: 20240012817Abstract: In some examples, a system identifies sub-portions of a database query, assigns identifiers to the identified sub-portions, and adds the identifiers to a data structure. The system generates a fingerprint representing the database query based on applying a fingerprint function on the data structure including the identifiers.Type: ApplicationFiled: July 7, 2022Publication date: January 11, 2024Inventors: Shine Mathew, Ashish Dange, Harsh Singh, Lakshmi Pathy S N
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Patent number: 11868353Abstract: In some examples, a system identifies sub-portions of a database query, assigns identifiers to the identified sub-portions, and adds the identifiers to a data structure. The system generates a fingerprint representing the database query based on applying a fingerprint function on the data structure including the identifiers.Type: GrantFiled: July 7, 2022Date of Patent: January 9, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Shine Mathew, Ashish Dange, Harsh Singh, Lakshmi Pathy
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Publication number: 20230244666Abstract: A process includes accessing a query that is associated with joining a fact table with a plurality of dimension tables. The fact table includes a primary key that includes a set of columns, which are covered by the dimension tables. The process includes determining a query plan for processing the query. The query plan has an associated join order. Determining the query plan includes determining a plurality of sets of the plurality of dimension tables, where each set includes dimension tables, which cover the set of columns of the primary key. Determining the query plan includes evaluating costs that are associated with joining subsets of the plurality of sets with the fact table. Based on the costs, a given subset of the plurality of subsets is selected. Determining the query plan includes constraining the join order based on the given subset so that the dimension tables of the given subset are joined before the fact table.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Shine Mathew, Ashish Dange, Harsh Singh, Javeed Pasha
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Publication number: 20220066605Abstract: The present disclosure relates to implementing scrolling controls within a software application. More particularly, the present disclosure relates to methods and systems of mapping and translating inputs received from one or more controllers or user interfaces communicatively coupled to a computing system or device on which a software application is being executed, to one or more instructions or events for implementing a scrolling event that the software application is configured to recognize.Type: ApplicationFiled: August 26, 2021Publication date: March 3, 2022Inventors: Harsh Singh, Pawan Kumar, Vasim Ali, Ravi Prakash
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Publication number: 20220066825Abstract: The invention presents methods, systems and computer program products for optimizing computer system resource utilization during in-game resource farming. The invention comprises (i) detecting a gameplay event that triggers switching from a resource farming mode to a non-resource farming mode, or for switching from a non-resource farming mode to a resource farming mode, in connection with a runtime instance of a gaining application software, (ii) identifying a guest operating system within which the runtime instance of the gaming application software is being executed, (iii) selecting a mode switching protocol implementable within the identified guest operating system, and (iv) switching the runtime instance of the gaming application software from a resource farming mode to a non-resource farming mode, or from a non-resource farming mode to a resource farming mode, by implementing the selected mode switching protocol.Type: ApplicationFiled: August 26, 2021Publication date: March 3, 2022Inventors: Suman Saraf, Ravi Prakash, Harsh Singh
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Publication number: 20190005469Abstract: The Collateral Management with Blockchain and Smart Contracts Apparatuses, Methods and Systems (“CMBSC”) transforms borrow transaction request inputs via CMBSC components into borrow transaction init notification, borrow transaction sync notification outputs. A borrow transaction request associated with a borrow transaction is obtained. Transaction attributes associated with the borrow transaction are stored in a database. The transaction process optimizer component is notified regarding the borrow transaction. A blockchain sync notification associated with the borrow transaction is obtained from the transaction process optimizer component. The stored transaction attributes associated with the borrow transaction are filtered. A smart contract associated with the borrow transaction is generated. The generated smart contract is sent to a blockchain node of a blockchain network. A smart contract notification associated with the smart contract is received.Type: ApplicationFiled: September 7, 2018Publication date: January 3, 2019Inventors: Sanjeev Dhupkar, Nishant Mehta, Harsh Singh, Thomas Stephen McGuire
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Patent number: 7817558Abstract: In one embodiment, a method includes detecting packet congestion in a network device that includes a switch, and a plurality of components operable to transmit and receive data packets from and to the switch. The method includes, in response to detecting packet congestion, transmitting an Ethernet pause frame to at least one of the plurality of components, the at least one component identified as a source of a data packet that caused the packet congestion, and transmitting a backward congestion notification (BCN) packet to the at least one component, the BCN packet including some data payload of the data packet that caused the packet congestion.Type: GrantFiled: November 8, 2006Date of Patent: October 19, 2010Assignee: Cisco Technology, Inc.Inventors: Pui Li, Harsh Singh
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Patent number: 7760647Abstract: In one embodiment, a flow control module aggregates indications of queuing resource utilization at devices attached to a switching fabric within a router and broadcasts that information out of band to all devices attached to the same switching fabric. When the flow control module identifies congestion at one of the attached devices according to the indications, the module may also cause a throttling of traffic sent to the congested device in addition to sending the out of band indication of the congestion to all the attached devices. Flow control modules for each of the attached devices provide local interrupts for reducing outbound traffic to a congested device according to the identification of that remote congestion.Type: GrantFiled: December 21, 2006Date of Patent: July 20, 2010Assignee: Cisco Technology, Inc.Inventors: Pui Li, Denis Claveloux, Joel Craig Naumann, Harsh Singh
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Publication number: 20080151919Abstract: In one embodiment, a flow control module aggregates indications of queuing resource utilization at devices attached to a switching fabric within a router and broadcasts that information out of band to all devices attached to the same switching fabric. When the flow control module identifies congestion at one of the attached devices according to the indications, the module may also cause a throttling of traffic sent to the congested device in addition to sending the out of band indication of the congestion to all the attached devices. Flow control modules for each of the attached devices provide local interrupts for reducing outbound traffic to a congested device according to the identification of that remote congestion.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: CISCO TECHNOLOGY, INC.Inventors: Pui Li, Denis Claveloux, Joel Craig Naumann, Harsh Singh
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Publication number: 20070268830Abstract: In one embodiment, a method includes detecting packet congestion in a network device that includes a switch, and a plurality of components operable to transmit and receive data packets from and to the switch. The method includes, in response to detecting packet congestion, transmitting an Ethernet pause frame to at least one of the plurality of components, the at least one component identified as a source of a data packet that caused the packet congestion, and transmitting a backward congestion notification (BCN) packet to the at least one component, the BCN packet including some data payload of the data packet that caused the packet congestion.Type: ApplicationFiled: November 8, 2006Publication date: November 22, 2007Applicant: CISCO TECHNOLOGY, INC.Inventors: Pui Li, Harsh Singh