Patents by Inventor Harsono S. Simka
Harsono S. Simka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11769686Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.Type: GrantFiled: September 29, 2016Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Harinath Reddy, Harsono S. Simka, Christopher D. Thomas
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Patent number: 11537898Abstract: A method and a system for material design utilizing machine learning are provided, where the underlying joint distribution p(S,P) of structure (S)-property (P) relationships is explicitly learned simultaneously and is utilized to directly generate samples (S,P) in a single step utilizing generative techniques, without any additional processing steps. The subspace of structures that meet or exceed the target for property P is then identified utilizing conditional generation of the distribution (e.g., p(P)), or through randomly generating a large number of samples (S,P) and filtering (e.g., selecting) those that meet target property criteria.Type: GrantFiled: February 24, 2020Date of Patent: December 27, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ganesh Hegde, Harsono S. Simka
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Publication number: 20210375662Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.Type: ApplicationFiled: September 29, 2016Publication date: December 2, 2021Applicant: Intel CorporationInventors: Harinath Reddy, Harsono S. Simka, Christopher D. Thomas
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Patent number: 11087055Abstract: A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.Type: GrantFiled: May 21, 2018Date of Patent: August 10, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ganesh Hegde, Harsono S. Simka, Chris Bowen
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Patent number: 11043454Abstract: A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.Type: GrantFiled: May 13, 2019Date of Patent: June 22, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ganesh Hegde, Harsono S. Simka
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Publication number: 20210103822Abstract: A method and a system for material design utilizing machine learning are provided, where the underlying joint distribution p(S,P) of structure (S)-property (P) relationships is explicitly learned simultaneously and is utilized to directly generate samples (S,P) in a single step utilizing generative techniques, without any additional processing steps. The subspace of structures that meet or exceed the target for property P is then identified utilizing conditional generation of the distribution (e.g., p(P)), or through randomly generating a large number of samples (S,P) and filtering (e.g., selecting) those that meet target property criteria.Type: ApplicationFiled: February 24, 2020Publication date: April 8, 2021Inventors: Ganesh Hegde, Harsono S. Simka
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Patent number: 10916513Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.Type: GrantFiled: June 26, 2019Date of Patent: February 9, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Rwik Sengupta, Mark S. Rodder
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Publication number: 20200235055Abstract: A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.Type: ApplicationFiled: May 13, 2019Publication date: July 23, 2020Inventors: Ganesh Hegde, Harsono S. Simka
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Publication number: 20200066645Abstract: Embodiments of the invention include a microelectronic device that includes a substrate having a layer of dielectric material that includes a feature with a depression, a Tungsten containing barrier liner layer formed in the depression of the feature, and a Cobalt conductive layer deposited on the Tungsten containing barrier liner layer in the depression of the feature. The Tungsten containing barrier liner layer provides adhesion for the Cobalt conductive layer.Type: ApplicationFiled: September 30, 2016Publication date: February 27, 2020Applicant: Intel CorporationInventors: Jason A. FARMER, Jeffrey S. LEIB, Michael L. MCSWINEY, Harsono S. SIMKA, Daniel B. BERGSTROM
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Publication number: 20190318998Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Inventors: Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Rwik Sengupta, Mark S. Rodder
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Patent number: 10381315Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.Type: GrantFiled: March 21, 2018Date of Patent: August 13, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Rwik Sengupta, Mark S. Rodder
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Publication number: 20190155977Abstract: A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.Type: ApplicationFiled: May 21, 2018Publication date: May 23, 2019Inventors: Ganesh Hegde, Harsono S. Simka, Chris Bowen
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Publication number: 20190148312Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.Type: ApplicationFiled: March 21, 2018Publication date: May 16, 2019Inventors: Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Rwik Sengupta, Mark S. Rodder
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Patent number: 9932671Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.Type: GrantFiled: March 27, 2014Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: James M. Blackwell, Patricio E. Romero, Scott B. Clendenning, Grant M. Kloster, Florian Gstrein, Harsono S. Simka, Paul A. Zimmerman, Robert L. Bristol
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Publication number: 20170058401Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.Type: ApplicationFiled: March 27, 2014Publication date: March 2, 2017Inventors: James M. BLACKWELL, Patricio E. ROMERO, Scott B. CLENDENNING, Grant M. KLOSTER, Florian GSTREIN, Harsono S. SIMKA, Paul A. ZIMMERMAN, Robert L. BRISTOL
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Patent number: 8779589Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.Type: GrantFiled: December 20, 2010Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
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Patent number: 8425987Abstract: A method including applying an electric charge to a substrate in a chamber; introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including applying a removable electric charge to a substrate; in the presence of the applied electric charge, introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent with an externally applied electric charge.Type: GrantFiled: December 31, 2008Date of Patent: April 23, 2013Assignee: Intel CorporationInventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Harsono S. Simka
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Patent number: 8344352Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.Type: GrantFiled: July 18, 2011Date of Patent: January 1, 2013Assignee: Intel CorporationInventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
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Patent number: 8319287Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.Type: GrantFiled: February 12, 2010Date of Patent: November 27, 2012Assignee: Intel CorporationInventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
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Publication number: 20120153478Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Inventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar