Patents by Inventor Haruhiko Ono

Haruhiko Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179214
    Abstract: A crew support system includes a communication terminal to collect information about a device on a watercraft and transmit the information, a server to receive the information from the communication terminal, and a client terminal to communicate with the server. The communication terminal includes a periodic transmission mode to transmit the information to the server in a periodic transmission cycle, and a high-speed transmission mode to transmit the information in a cycle shorter than the periodic transmission cycle. The server determines a status of the watercraft, and transmits information about measures to address the status, to the client terminal, based on the result of the determination. The client terminal provides the information received from the server to a user. The server determines whether or not a recovery operation by the crew is possible, and transmits information about the result of the determination regarding the recovery operation to the client terminal.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 30, 2024
    Inventors: Ryota INOUE, Toshihiko ONO, Akira TAKEUCHI, Yasuhiro KITAZAWA, Haruhiko HASHIMOTO, Yoshimasa KINOSHITA
  • Patent number: 7495264
    Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: February 24, 2009
    Assignee: NEC Corporation
    Inventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
  • Publication number: 20070090450
    Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.
    Type: Application
    Filed: December 7, 2006
    Publication date: April 26, 2007
    Applicant: NEC CORPORATION
    Inventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
  • Patent number: 7164169
    Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: January 16, 2007
    Assignee: NEC Corporation
    Inventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
  • Publication number: 20040171276
    Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is higher in a center portion in the film thickness direction than in an upper portion and in a lower portion.
    Type: Application
    Filed: November 10, 2003
    Publication date: September 2, 2004
    Inventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
  • Patent number: 6521930
    Abstract: In the case where a Ta2O5 thin film having double bond Ta═O is employed for a capacitative insulating film, Rapid Thermal Anneal in oxygen, and UV/O3 treatment are executed at suitable temperature and in suitable time. Whether or not absorption peak which appears in 2340 cm−1 exists and whether it is large or small are monitored by measuring a transmission infrared absorption spectrum of a Ta2O5 thin film with Fourier Transform Infrared Spectroscopy. In the case where a Ta2O5 thin film, in which an abundance ratio of oxygen in a three coordinate bonding state is large, is employed for a capacitative insulating film, an intensity ratio of each double peak which appears in 510 cm−1 and 570 cm−1 is measured as well, so that the film whose ratio (510/570) is larger than another one is used as Man character to improve quality of a film.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: February 18, 2003
    Assignee: NEC Corporation
    Inventor: Haruhiko Ono
  • Patent number: 6459126
    Abstract: A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: October 1, 2002
    Assignee: NEC Corporation
    Inventors: Tohru Mogami, Mitsuhiro Togo, Koji Watanabe, Toyoji Yamamoto, Nobuyuki Ikarashi, Kazutoshi Shiba, Toru Tatsumi, Haruhiko Ono
  • Publication number: 20020096721
    Abstract: A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.
    Type: Application
    Filed: May 11, 2001
    Publication date: July 25, 2002
    Applicant: NEC CORPORATION
    Inventors: Tohru Mogami, Mitsuhiro Togo, Koji Watanabe, Toyoji Yamamoto, Nobuyuki Ikarashi, Kazutoshi Shiba, Toru Tatsumi, Haruhiko Ono
  • Publication number: 20010050363
    Abstract: In the case where a Ta2O5 thin film having double bond Ta═O is employed for a capacitative insulating film, Rapid Thermal Anneal in oxygen and UV/O3 treatment are executed at suitable temperature and in suitable time. Whether or not absorption peak which appears in 2340 cm−1 exists and whether it is large or small are monitored by measuring a transmission infrared absorption spectrum of a Ta2O5 thin film with Fourier Transform Infrared Spectroscopy. In the case where a Ta2O5 thin film, in which an abundance ratio of oxygen in a three coordinate bonding state is large, is employed for a capacitative insulating film, an intensity ratio of each double peak which appears in 510 cm−1 and 570 cm−1 is measured as well, so that the film whose ratio (510/570) is larger than another one is used as an character to improve quality of a film.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 13, 2001
    Applicant: NEC Corporation
    Inventor: Haruhiko Ono
  • Patent number: 5972750
    Abstract: There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
  • Patent number: 5973355
    Abstract: There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa