Abstract: An electric bending endoscope comprises a bending portion arranged to an inserting portion and a bending driving unit which bends the bending portion. In the electric bending endoscope, the bending driving unit comprises a motor which generates driving force for bending the bending portion, a first unit which holds the motor, a driving force transmitting member which transmits the driving force of the motor, and a second unit which bends the bending portion by the driving force of the motor. The electric bending endoscope further comprises a first holding member which detachably supports, to the first unit, a rotating shaft arranged to the driving force transmitting member of the second unit.

Abstract: An electrically-bent endoscope includes a bend driving portion for bending a bending portion. The bend driving portion has a motor for generating driving force, a gear train for transmitting driving force generated in the motor, a sprocket for converting driving force of the motor to a back and forth movement of bending operation wires for bending the bending portion at the head portion of an inserting portion, and a clutch mechanism for connecting and disconnecting driving force transmitted from the gear train to the sprocket. The clutch mechanism includes a transmitting member for connecting and disconnecting the gear train and sprocket, a thrust mechanism for moving the transmitting member in the axial direction of the sprocket and a clutch operating member, connected to the thrust mechanism, for inputting instructions for connecting and disconnecting the gear train and the sprocket.

Abstract: A noise filter includes a plurality of magnetic sheets stacked one on another. The magnetic sheets are baked to form a layered product. A transmission line is arranged between the second and third magnetic sheets. The transmission line extends linearly in the longitudinal direction of the layered product. Two ground conductors have the second and third magnetic sheets therebetween. Signal electrodes connected to both ends of the transmission line are arranged adjacent to both ends, in the longitudinal direction, of the layered product. Grounding electrodes connected to the ground conductors are arranged in the middle positions, in the longitudinal direction, of the layered product. With the ground conductors being grounded, a signal passes through the transmission line, thus attenuating high-frequency noise using heat dissipation by the four magnetic sheets.

Abstract: In order to enable a plurality of access origins to effectively utilize a cache thereby to realize high-speed and stable processing, by measuring a frequency of access from the plurality of access origins, allocating a cache capacity based on the access frequency, and notifying an error, when it occurs, to an access origin having the allocation or to a predetermined access origin to process the error, there is provided a cache apparatus for enabling a plurality of access origins to make access to a cache memory. The cache apparatus comprises a unit for setting a cache capacity into which each access origin can charge data; a unit for charging data into an area within the set cache capacity in response to a request from each access origin based on the cache capacity; and a unit for reading data from the cache memory and notifying the data without depending on the set cache capacity when each access origin has made a reference request.

Abstract: In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.

Abstract: A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address.

Abstract: A system information storage section stores access information showing attributes for accessing a storage peculiar to a processor and storages peculiar to other processors by relating the access information to data. The system information storage section stores space identifying information for identifying each of plural kinds of virtual spaces allocated according to applications of the storages. A plurality of address translation sections translate virtual addresses into real addresses, corresponding to the plural kinds of virtual spaces on the basis of the access information. A selection section selects any one of the plurality of address translation sections on the basis of the space identifying information. A transfer control section reads the data of the storage on the basis of the real address obtained by the selected address translation section and transfers the data to other processors together with the access information and the space identifying information.

Abstract: A method and a processing apparatus for use in a parallel computer realizing a coordinate scheduling which does not degrade a throughput performance of a system. According to this invention, if a parallel process in execution gets into a parallel synchronization waiting state, the parallel process is deactivated so that allocation of the parallel process is inhibited, a process of another executable job is allocated, instead. If a setting condition is satisfied during the execution of another job, an interruption signal for a process in execution is generated to activate the parallel process in the parallel synchronization waiting state, thereby resuming allocation of this parallel process. This invention may be applied to a parallel computer system of a distributed main storage MIMD type which implements plural tasks in parallel by plural PEs.

Abstract: A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.

Abstract: A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.

Abstract: A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information.

Abstract: A transfer request queue control system for a parallel computer system includes a plurality of processing units each having a main storage storing instructions and data. An instruction processor reads the instructions from the main storage and executes the instructions. A transfer processor performs data transfers in packets, each comprising a header and body data and each data transfer comprising one or more packets. A network couples transmitting and receiving processing units, which are to perform a data transfer based on information included in the header of each packet, the header information being related to a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor performs parallel processing by making a data transfer between the main storage and the network in successive packets, depending on the attribute of the memory access.

Abstract: A parallel processing system including a plurality of processing units each having a main storage storing instructions and data, an instruction processor reading the instructions from the main storage and executing the instructions, and a transfer processor for making a data transfer in units of a packet which is made up of a header and body data. The parallel processing system further includes a network coupling two processing units which are to make the data transfer based on information included in the header of the packet, where the header includes information related to at least a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor carries out a parallel process for each user process by making a data transfer between the main storage and the network in units of the packet depending on the attribute of the memory access.

Abstract: An apparatus in which ultrasonic vibrations or acoustic emissions are detected includes a rotating shaft 21 having a dressing wheel 31 mounted on one end, and a detection liquid supply unit 41 disposed at the end face of the wheel and/or shaft so as to form a gap S therebetween and to supply detection liquid toward the rotational center of the wheel to form a detection liquid membrane in the gap. An AE sensor 43 is provided integrally with the detection liquid supply unit and detects the ultrasonic vibrations or acoustic emissions of the wheel and/or shaft through the detection liquid membrane formed in the gap.

Abstract: This invention relates to an abnormal packet processing system, and is directed to minimize processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. This data processing system includes a plurality of processing units connected through an interconnection. At least one of the processing units is a transmitting processor which includes a unit for detecting an abnormality of a data packet during transmission of the data packet to a receiving processor; and a unit for adding abnormality report data to the data packet being transmitted and sending the data packet with the abnormality report data to the receiving processor, or, in the alternate, inhibiting transmission of the abnormal packet.

Abstract: Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data.

Abstract: In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.

Abstract: A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit.

Abstract: A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register.

Abstract: An interruption processing system enables a basic CPU resource using process to be executed asynchronously, enabling an interruption handler to be easily created. Interruption handling of the basic CPU resource using process interruption handler to be executed asynchronously enables corresponding interruption handler process is terminated for a CPU resource using process dependent interruption factor. The interruption processing system comprises a queuing unit for determining whether an instruction stored in an instruction buffer designates a synchronous process or an asynchronous process and for queuing the instruction when it is an asynchronous process.