Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers aligned in a first direction with a space in between; a first plug penetrating the first conductive layers; a second conductive layer below the first conductive layers, the second conductive layer being coupled to a lower end of the first plug; a first transistor below the first conductive layers; a second transistor in a second region between the first transistor and a first region below the second conductive layer, the second transistor having a gate electrically coupled to the first transistor and a drain electrically coupled to the first transistor; and a third transistor in the second region, the third transistor having a source and a drain electrically coupled to each other.

Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.

Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.