Abstract: The disclosure concerns an inter-base station frame synchronization system for use in a mobile communication system having at least one master base station and a plurality of slave base stations. The master base station is arranged to transmit a control channel signal to the slave base stations located around the master base station in synchronization with a reference frame timing. The slave base stations set a control channel signal observation period. The slave base stations are arranged to generate frame timing based on timings of a received control channel signal from the master base station or other slave base stations when the received control channel signal is received during the control channel signal observation period.

Abstract: An inter-base station frame synchronization system for use in a mobile communication system includes at least one master base station and a plurality of slave base stations. The master base station is provided with time information receiving means for receiving time information with high precision externally supplied, reference frame timing generation means for generating a reference frame timing on the basis of the time information, and first control channel signal transmission means for transmitting a control channel signal to the slave base stations in synchronism with the reference frame timing.

Abstract: A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.

Abstract: A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.

Abstract: A local area network in which a plurality of local equipments, each having one or more terminals connected thereto, are connected to different points of a common signal transmission path leading from a central equipment. The central equipment sends out data signals addressed to the local equipments to the common path on a time division basis. Each local equipment sends a data signal from the terminals to the central equipment in response to the reception of a self-addressed data signal from the central equipment. To avoid a collision or overspace between the data signals transmitted from local equipments the central equipment sends out control signals addressed to the local equipments in response to signals from the local equipments. Each local equipment controls the transmission start timing of the data signal to the central equipment in response to the self-addressed control signal.

Abstract: A signal multiplex transmission system has predetermined work stations included in a plurality of terminal units which respectively process data in predetermined forms, and a private branch exchange or PBX. A transmission line is connected between the predetermined work stations and the PBX to commonly transmit frequency-multiplexed data from the PBX to the predetermined work stations. A separation filter separates first multiplexed signals supplied from the predetermined work stations from second multiplexed signals from other work stations and supplies the separated first multiplexed signals to the PBX independently of the second multiplexed signals, which signals are amplified by an amplifier. A mixer is connected to the PBX, the amplifier and a reception line. The first and second multiplexed signals are mixed by the mixer, and composite data is sent onto the reception line. The signal lines are used to transmit the multiplexed signals having the same frequency band.

Abstract: A transversal equalizer has a transversal filter which performs a convolution of an unequalized signal and a tap weight. In the automatic equalization mode, the tap weight is updated according to the result of a correlation of the unequalized signal and an error signal, and the updated tap weight is applied to the transversal filter. In the fixed equalization mode, a fixed tap weight stored in a memory is applied to the transversal filter.

Abstract: A clock synchronization signal generating circuit includes a clock synchronizing circuit having a scale variable counter for counting a source clock signal from a source clock generator and a control circuit for controlling the scale of counter responsive to the phase difference between an input clock signal supplied from a digital operation system and an output signal from the scale variable counter, and a clock circuit including a counter for counting in n-scale mode a source clock signal from the source clock generator. The scale variable counter is selectively set to (n-1)-, n- or (n+1)-scale mode responsive to the control signal from the control circuit to generate an output signal which is clock-synchronized with the input clock signal.

Abstract: A periodic function wave generator is provided in a digital phase synchronizing circuit which comprises a memory circuit for storing the values of n phases obtained by equally dividing one period of a sine wave by 4n and each having a phase .theta.=90.degree./n(i+0.5), where n represents an integer and i is an integer of from 0 to n-1, a circuit for designating a predetermined one of these phases in one period, a circuit for converting an address read out of the memory circuit into one of the n phases in accordance with one of the ranges of 0.degree. to 90.degree., 90.degree. to 180.degree., 180.degree. to 270.degree. and 270.degree. to 360.degree. and a circuit for inverting the sign of the output of the memory circuit in accordance with the particular range in which the designated phase falls.

Abstract: A digital filter system comprising a plurality of digital filters having respective counters operated by the same clock signal, at least one of these digital filters including an operation control section having a counter to count the clock signal and be cleared with a clear signal and a circuit to produce a control signal according to the content of the aforesaid counter, an ROM to provide predetermined coefficients according to the output of the arithmetic control section, an arithmetic section to carry out predetermined arithmetic operations with the above predetermined coefficients under the control of the control signal received from the arithmetic control section, a delay memory section, a switching device controlled for switching to execute the arithmetic operations under the control of the control signal received at the time of execution of the operations, and a circuit to produce a synchronizing signal at the time of the end of the operations in the aforesaid filter, said synchronizing signal being s

Abstract: The detector is provided with an input control circuit supplied with a first input for extracting a carrier wave from a modulated wave and a second input for demodulating the modulated wave and controlled to produce the first and second inputs on the time division basis, a reference wave generating circuit which produces a sine wave or a cosine wave as a reference wave and produces amplitude values corresponding to designated phases, and a time division multiplying circuit which multiplies the outputs of the input control circuit with the amplitude values on the time division basis for producing the demodulated signal.