Patents by Inventor Haruko Tadokoro
Haruko Tadokoro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6754133Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.Type: GrantFiled: August 30, 2002Date of Patent: June 22, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Patent number: 6680869Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.Type: GrantFiled: April 12, 2002Date of Patent: January 20, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takahiro Sonoda, Takeshi Sakata, Sadayuki Morita, Yoshinobu Nakagome, Haruko Tadokoro, Osamu Nagashima
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Patent number: 6549484Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: GrantFiled: September 28, 2001Date of Patent: April 15, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Publication number: 20030002316Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.Type: ApplicationFiled: August 30, 2002Publication date: January 2, 2003Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Publication number: 20020118575Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.Type: ApplicationFiled: April 12, 2002Publication date: August 29, 2002Applicant: Hitachi, Ltd.Inventors: Takahiro Sonoda, Takeshi Sakata, Sadayuki Morita, Yoshinobu Nakagome, Haruko Tadokoro, Osamu Nagashima
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Patent number: 6407963Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.Type: GrantFiled: October 13, 2000Date of Patent: June 18, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., LtdInventors: Takahiro Sonoda, Takeshi Sakata, Sadayuki Morita, Yoshinobu Nakagome, Haruko Tadokoro, Osamu Nagashima
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Publication number: 20020018396Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: ApplicationFiled: September 28, 2001Publication date: February 14, 2002Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Patent number: 6335901Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: GrantFiled: March 20, 2000Date of Patent: January 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima